69#include "llvm/IR/IntrinsicsPowerPC.h"
103#define DEBUG_TYPE "ppc-lowering"
140 bool isPPC64 = Subtarget.
isPPC64();
198 if (!Subtarget.
hasSPE()) {
217 if (isPPC64 || Subtarget.
hasFPCVT()) {
345 !(TM.Options.UnsafeFPMath && Subtarget.
hasFRSQRTE() &&
350 !(TM.Options.UnsafeFPMath && Subtarget.
hasFRSQRTES() &&
446 if (TM.Options.UnsafeFPMath) {
639 if (VT.getSizeInBits() <= 128 && VT.getScalarSizeInBits() <= 64) {
850 if (TM.Options.UnsafeFPMath) {
1084 if (Subtarget.
hasQPX()) {
1222 if (TM.Options.UnsafeFPMath) {
1395 VTy->getPrimitiveSizeInBits().getFixedSize() >= 256)
1397 else if (VTy->getPrimitiveSizeInBits().getFixedSize() >= 128 &&
1406 for (
auto *EltTy : STy->elements()) {
1426 return Alignment.
value();
1434 return Subtarget.
hasSPE();
1466 return "PPCISD::FP_TO_UINT_IN_VSR,";
1468 return "PPCISD::FP_TO_SINT_IN_VSR";
1475 return "PPCISD::XXSPLTI_SP_TO_DP";
1477 return "PPCISD::XXSPLTI32DX";
1512 return "PPCISD::SCALAR_TO_VECTOR_PERMUTED";
1514 return "PPCISD::ANDI_rec_1_EQ_BIT";
1516 return "PPCISD::ANDI_rec_1_GT_BIT";
1531 return "PPCISD::ST_VSR_SCAL_INT";
1605 return CFP->getValueAPF().isZero();
1610 return CFP->getValueAPF().isZero();
1618 return Op < 0 || Op == Val;
1630 if (ShuffleKind == 0) {
1633 for (
unsigned i = 0;
i != 16; ++
i)
1636 }
else if (ShuffleKind == 2) {
1639 for (
unsigned i = 0;
i != 16; ++
i)
1642 }
else if (ShuffleKind == 1) {
1643 unsigned j =
IsLE ? 0 : 1;
1644 for (
unsigned i = 0;
i != 8; ++
i)
1661 if (ShuffleKind == 0) {
1664 for (
unsigned i = 0;
i != 16;
i += 2)
1668 }
else if (ShuffleKind == 2) {
1671 for (
unsigned i = 0;
i != 16;
i += 2)
1675 }
else if (ShuffleKind == 1) {
1676 unsigned j =
IsLE ? 0 : 2;
1677 for (
unsigned i = 0;
i != 8;
i += 2)
1703 if (ShuffleKind == 0) {
1706 for (
unsigned i = 0;
i != 16;
i += 4)
1712 }
else if (ShuffleKind == 2) {
1715 for (
unsigned i = 0;
i != 16;
i += 4)
1721 }
else if (ShuffleKind == 1) {
1722 unsigned j =
IsLE ? 0 : 4;
1723 for (
unsigned i = 0;
i != 8;
i += 4)
1743 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
1744 "Unsupported merge size!");
1746 for (
unsigned i = 0;
i != 8/UnitSize; ++
i)
1747 for (
unsigned j = 0;
j != UnitSize; ++
j) {
1766 if (ShuffleKind == 1)
1768 else if (ShuffleKind == 2)
1773 if (ShuffleKind == 1)
1775 else if (ShuffleKind == 0)
1791 if (ShuffleKind == 1)
1793 else if (ShuffleKind == 2)
1798 if (ShuffleKind == 1)
1800 else if (ShuffleKind == 0)
1854 for (
unsigned i = 0;
i < 2; ++
i)
1855 for (
unsigned j = 0;
j < 4; ++
j)
1882 if (ShuffleKind == 1)
1884 else if (ShuffleKind == 2)
1891 if (ShuffleKind == 1)
1893 else if (ShuffleKind == 0)
1916 for (
i = 0;
i != 16 &&
SVOp->getMaskElt(
i) < 0; ++
i)
1919 if (
i == 16)
return -1;
1923 unsigned ShiftAmt =
SVOp->getMaskElt(
i);
1924 if (ShiftAmt <
i)
return -1;
1929 if ((ShuffleKind == 0 && !isLE) || (ShuffleKind == 2 && isLE)) {
1931 for (++
i;
i != 16; ++
i)
1934 }
else if (ShuffleKind == 1) {
1936 for (++
i;
i != 16; ++
i)
1943 ShiftAmt = 16 - ShiftAmt;
1953 EltSize <= 8 &&
"Can only handle 1,2,4,8 byte element sizes");
1957 if (
N->getMaskElt(0) % EltSize != 0)
1970 for (
unsigned i = 1;
i != EltSize; ++
i)
1974 for (
unsigned i = EltSize, e = 16;
i != e;
i += EltSize) {
1975 if (
N->getMaskElt(
i) < 0)
continue;
1976 for (
unsigned j = 0;
j != EltSize; ++
j)
1977 if (
N->getMaskElt(
i+
j) !=
N->getMaskElt(
j))
1994 assert((Width == 2 || Width == 4 || Width == 8 || Width == 16) &&
1995 "Unexpected element width.");
2008 for (
unsigned int j = 1;
j < Width; ++
j) {
2025 unsigned M0 =
N->getMaskElt(0) / 4;
2026 unsigned M1 =
N->getMaskElt(4) / 4;
2027 unsigned M2 =
N->getMaskElt(8) / 4;
2028 unsigned M3 =
N->getMaskElt(12) / 4;
2035 if ((
M0 > 3 &&
M1 == 1 &&
M2 == 2 &&
M3 == 3) ||
2036 (
M0 < 4 &&
M1 == 5 &&
M2 == 6 &&
M3 == 7)) {
2043 if ((
M1 > 3 &&
M0 == 0 &&
M2 == 2 &&
M3 == 3) ||
2044 (
M1 < 4 &&
M0 == 4 &&
M2 == 6 &&
M3 == 7)) {
2051 if ((
M2 > 3 &&
M0 == 0 &&
M1 == 1 &&
M3 == 3) ||
2052 (
M2 < 4 &&
M0 == 4 &&
M1 == 5 &&
M3 == 7)) {
2059 if ((
M3 > 3 &&
M0 == 0 &&
M1 == 1 &&
M2 == 2) ||
2060 (
M3 < 4 &&
M0 == 4 &&
M1 == 5 &&
M2 == 6)) {
2069 if (
N->getOperand(1).isUndef()) {
2095 bool &Swap,
bool IsLE) {
2102 unsigned M0 =
N->getMaskElt(0) / 4;
2103 unsigned M1 =
N->getMaskElt(4) / 4;
2104 unsigned M2 =
N->getMaskElt(8) / 4;
2105 unsigned M3 =
N->getMaskElt(12) / 4;
2109 if (
N->getOperand(1).isUndef()) {
2110 assert(
M0 < 4 &&
"Indexing into an undef vector?");
2111 if (
M1 != (
M0 + 1) % 4 ||
M2 != (
M1 + 1) % 4 ||
M3 != (
M2 + 1) % 4)
2120 if (
M1 != (
M0 + 1) % 8 ||
M2 != (
M1 + 1) % 8 ||
M3 != (
M2 + 1) % 8)
2124 if (
M0 == 0 ||
M0 == 7 ||
M0 == 6 ||
M0 == 5) {
2130 }
else if (
M0 == 4 ||
M0 == 3 ||
M0 == 2 ||
M0 == 1) {
2140 if (
M0 == 0 ||
M0 == 1 ||
M0 == 2 ||
M0 == 3) {
2145 }
else if (
M0 == 4 ||
M0 == 5 ||
M0 == 6 ||
M0 == 7) {
2162 for (
int i = 0;
i < 16;
i += Width)
2163 if (
N->getMaskElt(
i) !=
i + Width - 1)
2194 bool &Swap,
bool IsLE) {
2201 unsigned M0 =
N->getMaskElt(0) / 8;
2202 unsigned M1 =
N->getMaskElt(8) / 8;
2203 assert(((
M0 |
M1) < 4) &&
"A mask element out of bounds?");
2207 if (
N->getOperand(1).isUndef()) {
2208 if ((
M0 |
M1) < 2) {
2209 DM =
IsLE ? (((~M1) & 1) << 1) + ((~
M0) & 1) : (
M0 << 1) + (
M1 & 1);
2217 if (
M0 > 1 &&
M1 < 2) {
2227 DM = (((~M1) & 1) << 1) + ((~
M0) & 1);
2232 }
else if (
M0 > 1 &&
M1 < 2) {
2240 DM = (
M0 << 1) + (
M1 & 1);
2254 return (16 / EltSize) - 1 - (
SVOp->getMaskElt(0) / EltSize);
2256 return SVOp->getMaskElt(0) / EltSize;
2270 unsigned EltSize = 16/
N->getNumOperands();
2271 if (EltSize < ByteSize) {
2272 unsigned Multiple = ByteSize/EltSize;
2277 for (
unsigned i = 0, e =
N->getNumOperands();
i != e; ++
i) {
2278 if (
N->getOperand(
i).isUndef())
continue;
2322 for (
unsigned i = 0, e =
N->getNumOperands();
i != e; ++
i) {
2323 if (
N->getOperand(
i).isUndef())
continue;
2324 if (!
OpVal.getNode())
2326 else if (
OpVal !=
N->getOperand(
i))
2337 assert(
CN->getValueType(0) ==
MVT::f32 &&
"Only one legal FP vector type!");
2366 EVT VT =
N->getValueType(0);
2374 for (
i = 0;
i != 4 &&
SVOp->getMaskElt(
i) < 0; ++
i)
2377 if (
i == 4)
return -1;
2381 unsigned ShiftAmt =
SVOp->getMaskElt(
i);
2382 if (ShiftAmt <
i)
return -1;
2386 for (++
i;
i != 4; ++
i)
2463 }
else if (
N.getOpcode() ==
ISD::OR) {
2473 if (
LHSKnown.Zero.getBoolValue()) {
2558 }
else if (
N.getOperand(1).getOpcode() ==
PPCISD::Lo) {
2561 &&
"Cannot handle constant offsets yet!");
2570 }
else if (
N.getOpcode() ==
ISD::OR) {
2603 CN->getValueType(0));
2609 (int64_t)
CN->getZExtValue() == (
int)
CN->getZExtValue()) &&
2612 int Addr = (int)
CN->getZExtValue();
2619 unsigned Opc =
CN->getValueType(0) ==
MVT::i32 ? PPC::LIS : PPC::LIS8;
2653 !
N.getOperand(1).hasOneUse() || !
N.getOperand(0).hasOneUse())) {
2699 if (!
MemVT.isSimple())
2701 switch(
MemVT.getSimpleVT().SimpleTy) {
2705 if (!ST.hasP8Vector())
2710 if (!ST.hasP9Vector())
2723 if (UI.getUse().get().getResNo() == 0 &&
2745 Ptr = LD->getBasePtr();
2746 VT = LD->getMemoryVT();
2747 Alignment = LD->getAlignment();
2749 Ptr = ST->getBasePtr();
2750 VT = ST->getMemoryVT();
2751 Alignment = ST->getAlignment();
2871 const bool Is64Bit = Subtarget.
isPPC64();
2902 return getTOCEntry(DAG,
SDLoc(CP),
GA);
2912 return getTOCEntry(DAG,
SDLoc(CP),
GA);
2990 return getTOCEntry(DAG,
SDLoc(JT),
GA);
3059 bool is64bit = Subtarget.
isPPC64();
3089 if (!
TM.isPositionIndependent())
3171 return getTOCEntry(DAG,
DL,
GA);
3182 return getTOCEntry(DAG,
DL,
GA);
3228 if (
C->isAllOnesValue() ||
C->isNullValue())
3239 EVT VT =
Op.getValueType();
3249 EVT VT =
Node->getValueType(0);
3302 DAG.getConstant(8, dl,
MVT::i32), ISD::
SETLT);
3307 DAG.getConstant(VT.isInteger() ? 4 : 8, dl,
3322 DAG.getConstant(VT ==
MVT::i64 ? 2 : 1, dl,
3347 assert(!Subtarget.
isPPC64() &&
"LowerVACOPY is PPC32 only");
3351 return DAG.
getMemcpy(
Op.getOperand(0), Op,
Op.getOperand(1),
Op.getOperand(2),
3362 return Op.getOperand(0);
3383 Entry.
Ty = IntPtrTy;
3384 Entry.Node =
Trmp;
Args.push_back(Entry);
3387 Entry.Node = DAG.
getConstant(isPPC64 ? 48 : 40, dl,
3388 isPPC64 ?
MVT::i64 :
MVT::i32);
3389 Args.push_back(Entry);
3391 Entry.Node =
FPtr;
Args.push_back(Entry);
3392 Entry.Node =
Nest;
Args.push_back(Entry);
3396 CLI.setDebugLoc(dl).setChain(Chain).setLibCallee(
3451 uint64_t FrameOffset =
PtrVT.getSizeInBits()/8;
3457 uint64_t FPROffset = 1;
3490static const MCPhysReg FPR[] = {PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5,
3491 PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10,
3492 PPC::F11, PPC::F12, PPC::F13};
3496 PPC::QF1, PPC::QF2, PPC::QF3, PPC::QF4, PPC::QF5, PPC::QF6, PPC::QF7,
3497 PPC::QF8, PPC::QF9, PPC::QF10, PPC::QF11, PPC::QF12, PPC::QF13};
3504 if (Flags.isByVal())
3505 ArgSize = Flags.getByValSize();
3509 if (!Flags.isInConsecutiveRegs())
3527 Alignment =
Align(16);
3531 Alignment =
Align(32);
3534 if (Flags.isByVal()) {
3535 auto BVAlign = Flags.getNonZeroByValAlign();
3539 "ByVal alignment is not a multiple of the pointer size");
3546 if (Flags.isInConsecutiveRegs()) {
3566 unsigned LinkageSize,
3584 if (Flags.isInConsecutiveRegsLast())
3593 if (!Flags.isByVal()) {
3619 unsigned NumBytes) {
3623SDValue PPCTargetLowering::LowerFormalArguments(
3628 return LowerFormalArguments_AIX(Chain, CallConv, isVarArg, Ins, dl, DAG,
3631 return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins, dl, DAG,
3634 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins, dl, DAG,
3637 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins, dl, DAG,
3641SDValue PPCTargetLowering::LowerFormalArguments_32SVR4(
3692 CCInfo.AllocateStack(LinkageSize,
PtrAlign);
3694 CCInfo.PreAnalyzeFormalArguments(Ins);
3697 CCInfo.clearWasPPCF128();
3699 for (
unsigned i = 0, e =
ArgLocs.size();
i !=
e; ++
i) {
3703 if (
VA.isRegLoc()) {
3705 EVT ValVT =
VA.getValVT();
3712 RC = &PPC::GPRCRegClass;
3716 RC = &PPC::VSSRCRegClass;
3717 else if (Subtarget.
hasSPE())
3718 RC = &PPC::GPRCRegClass;
3720 RC = &PPC::F4RCRegClass;
3724 RC = &PPC::VSFRCRegClass;
3725 else if (Subtarget.
hasSPE())
3727 RC = &PPC::GPRCRegClass;
3729 RC = &PPC::F8RCRegClass;
3734 RC = &PPC::VRRCRegClass;
3737 RC = Subtarget.
hasQPX() ? &PPC::QSRCRegClass : &PPC::VRRCRegClass;
3741 RC = &PPC::VRRCRegClass;
3744 RC = &PPC::QFRCRegClass;
3747 RC = &PPC::QBRCRegClass;
3755 assert(
i + 1 < e &&
"No second half of double precision argument");
3772 InVals.push_back(ArgValue);
3778 unsigned ArgSize =
VA.getLocVT().getStoreSize();
3780 unsigned ObjSize =
VA.getValVT().getStoreSize();
3806 unsigned MinReservedArea =
CCByValInfo.getNextStackOffset();
3807 MinReservedArea = std::max(MinReservedArea, LinkageSize);
3823 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
3824 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
3829 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
3846 CCInfo.getNextStackOffset(),
true));
3902 const SDLoc &dl)
const {
3906 else if (Flags.isZExt())
3913SDValue PPCTargetLowering::LowerFormalArguments_64SVR4(
3926 "fastcc not supported on varargs functions");
3936 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
3937 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
3940 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
3941 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
3957 unsigned NumBytes = LinkageSize;
3960 for (
unsigned i = 0, e =
Ins.size();
i !=
e; ++
i) {
3961 if (Ins[
i].Flags.isNest())
3981 for (
unsigned ArgNo = 0, e =
Ins.size(); ArgNo !=
e; ++ArgNo) {
3989 if (Ins[ArgNo].isOrigArg()) {
4016 if (Flags.isByVal()) {
4017 assert(Ins[ArgNo].isOrigArg() &&
"Byval arguments cannot be implicit");
4023 ObjSize = Flags.getByValSize();
4035 InVals.push_back(
FIN);
4058 if (!isLittleEndian) {
4062 InVals.push_back(
Arg);
4093 InVals.push_back(
FIN);
4117 switch (
ObjectVT.getSimpleVT().SimpleTy) {
4122 if (Flags.isNest()) {
4124 unsigned VReg = MF.
addLiveIn(PPC::X11, &PPC::G8RCRegClass);
4167 ? &PPC::VSSRCRegClass
4171 ? &PPC::VSFRCRegClass
4190 DAG.getConstant(32, dl,
MVT::i32));
4208 if (Flags.isInConsecutiveRegsLast())
4220 if (!Subtarget.
hasQPX()) {
4239 "Invalid QPX parameter type");
4249 switch (
ObjectVT.getSimpleVT().SimpleTy) {
4250 case MVT::v4f64: RC = &PPC::QFRCRegClass;
break;
4251 case MVT::v4f32: RC = &PPC::QSRCRegClass;
break;
4252 default: RC = &PPC::QBRCRegClass;
break;
4278 InVals.push_back(
ArgVal);
4282 unsigned MinReservedArea;
4286 MinReservedArea = LinkageSize;
4331SDValue PPCTargetLowering::LowerFormalArguments_Darwin(
4353 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
4354 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
4357 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4358 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4361 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4362 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4381 if (!isVarArg && !isPPC64) {
4382 for (
unsigned ArgNo = 0, e =
Ins.size(); ArgNo !=
e;
4387 if (Flags.isByVal()) {
4389 unsigned ObjSize = Flags.getByValSize();
4396 switch(
ObjectVT.getSimpleVT().SimpleTy) {
4431 for (
unsigned ArgNo = 0, e =
Ins.size(); ArgNo !=
e; ++ArgNo) {
4438 if (Ins[ArgNo].isOrigArg()) {
4447 if (isVarArg || isPPC64) {
4448 MinReservedArea = ((MinReservedArea+15)/16)*16;
4461 if (Flags.isByVal()) {
4462 assert(Ins[ArgNo].isOrigArg() &&
"Byval arguments cannot be implicit");
4465 ObjSize = Flags.getByValSize();
4475 InVals.push_back(
FIN);
4522 switch (
ObjectVT.getSimpleVT().SimpleTy) {
4609 if (!isVarArg && !isPPC64) {
4634 InVals.push_back(
ArgVal);
4639 MinReservedArea = ((MinReservedArea+15)/16)*16;
4644 MinReservedArea = std::max(MinReservedArea, LinkageSize + 8 *
PtrByteSize);
4694 unsigned ParamSize) {
4696 if (!isTailCall)
return 0;
4717 "PC Relative callers do not have a TOC and cannot share a TOC Base");
4733 if (!TM.shouldAssumeDSOLocal(*Caller->getParent(), GV))
4758 if (
STICallee->isUsingPCRelativeCalls())
4777 if (TM.getFunctionSections() || GV->
hasComdat() || Caller->hasComdat() ||
4781 if (
F->getSectionPrefix() != Caller->getSectionPrefix())
4797 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4798 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4801 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4802 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4810 unsigned NumBytes = LinkageSize;
4815 if (Param.Flags.isNest())
continue;
4873bool PPCTargetLowering::IsEligibleForTailCallOptimization_64SVR4(
4882 if (isVarArg)
return false;
4961PPCTargetLowering::IsEligibleForTailCallOptimization(
SDValue Callee,
4977 for (
unsigned i = 0;
i !=
Ins.size();
i++) {
4979 if (Flags.isByVal())
return false;
4989 return G->getGlobal()->hasHiddenVisibility()
4990 ||
G->getGlobal()->hasProtectedVisibility();
5000 if (!
C)
return nullptr;
5002 int Addr =
C->getZExtValue();
5003 if ((Addr & 3) != 0 ||
5009 (
int)
C->getZExtValue() >> 2,
SDLoc(Op),
5016struct TailCallArgumentInfo {
5021 TailCallArgumentInfo() =
default;
5052 bool isPPC64 = Subtarget.
isPPC64();
5053 int SlotSize = isPPC64 ? 8 : 4;
5076 TailCallArgumentInfo
Info;
5078 Info.FrameIdxOp =
FIN;
5086SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(
5092 LROpOut = getReturnAddrFrameIndex(DAG);
5110 Flags.getNonZeroByValAlign(),
false,
false,
false,
5171 return G->getGlobal()->getValueType()->isFunctionTy();
5177SDValue PPCTargetLowering::LowerCallResult(
5191 for (
unsigned i = 0, e =
RVLocs.size();
i !=
e; ++
i) {
5193 assert(
VA.isRegLoc() &&
"Can only return in registers!");
5200 Chain =
Lo.getValue(1);
5205 Chain =
Hi.getValue(1);
5217 switch (
VA.getLocInfo()) {
5235 InVals.push_back(Val);
5338 [&](
StringRef FuncName,
bool IsDeclaration,
5343 Context.getOrCreateSymbol(
Twine(
".") +
Twine(FuncName)));
5377 const char *SymName = S->getSymbol();
5403 "Expected a CALLSEQ_STARTSDNode.");
5478 const unsigned Alignment = Subtarget.
isPPC64() ? 8 : 4;
5482 Alignment, MMOFlags);
5502 Chain =
TOCVal.getValue(0);
5503 Glue =
TOCVal.getValue(1);
5508 "Nest parameter is not supported on AIX.");
5511 Chain =
EnvVal.getValue(0);
5512 Glue =
EnvVal.getValue(1);
5527 const bool IsPPC64 = Subtarget.
isPPC64();
5532 Ops.push_back(Chain);
5538 assert(!
CFlags.IsPatchPoint &&
"Patch point calls are not indirect.");
5567 Ops.push_back(DAG.
getRegister(IsPPC64 ? PPC::CTR8 : PPC::CTR, RegVT));
5595 assert(Mask &&
"Missing call preserved mask for calling convention");
5600 Ops.push_back(Glue);
5603SDValue PPCTargetLowering::FinishCall(
5622 dl,
CFlags.HasNest, Subtarget);
5641 "Expecting a global address, external symbol, absolute value, "
5642 "register or an indirect tail call when PC Relative calls are "
5646 "Unexpected call opcode for a tail call.");
5669 return LowerCallResult(Chain, Glue,
CFlags.CallConv,
CFlags.IsVarArg, Ins, dl,
5693 isTailCall = IsEligibleForTailCallOptimization_64SVR4(
5694 Callee, CallConv, CB, isVarArg, Outs, Ins, DAG);
5696 isTailCall = IsEligibleForTailCallOptimization(
Callee, CallConv, isVarArg,
5711 "Callee should be an llvm::Function object.");
5714 <<
"\nTCO callee: ");
5721 "site marked musttail");
5739 return LowerCall_64SVR4(Chain,
Callee,
CFlags, Outs, OutVals, Ins, dl, DAG,
5743 return LowerCall_32SVR4(Chain,
Callee,
CFlags, Outs, OutVals, Ins, dl, DAG,
5747 return LowerCall_AIX(Chain,
Callee,
CFlags, Outs, OutVals, Ins, dl, DAG,
5750 return LowerCall_Darwin(Chain,
Callee,
CFlags, Outs, OutVals, Ins, dl, DAG,
5754SDValue PPCTargetLowering::LowerCall_32SVR4(
5765 const bool IsVarArg =
CFlags.IsVarArg;
5766 const bool IsTailCall =
CFlags.IsTailCall;
5797 CCInfo.PreAnalyzeCallOperands(Outs);
5803 unsigned NumArgs = Outs.size();
5805 for (
unsigned i = 0;
i != NumArgs; ++
i) {
5806 MVT ArgVT = Outs[
i].VT;
5810 if (Outs[
i].IsFixed) {
5820 errs() <<
"Call operand #" <<
i <<
" has unhandled type "
5830 CCInfo.clearWasPPCF128();
5844 unsigned NumBytes =
CCByValInfo.getNextStackOffset();
5858 Chain = EmitTailCallLoadFPAndRetAddr(DAG,
SPDiff, Chain,
LROp,
FPOp, dl);
5881 if (Flags.isByVal()) {
5925 if (
VA.isRegLoc()) {
5993SDValue PPCTargetLowering::createMemcpyOutsideCallSeq(
6000 int64_t FrameSize =
CallSeqStart.getConstantOperandVal(1);
6008SDValue PPCTargetLowering::LowerCall_64SVR4(
6017 unsigned NumOps = Outs.size();
6038 "fastcc not supported on varargs functions");
6045 unsigned NumBytes = LinkageSize;
6050 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
6051 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
6054 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
6055 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
6073 for (
unsigned i = 0;
i !=
NumOps; ++
i) {
6074 if (Outs[
i].Flags.isNest())
continue;
6093 for (
unsigned i = 0;
i !=
NumOps; ++
i) {
6095 EVT ArgVT = Outs[
i].VT;
6102 if (Flags.isByVal()) {
6128 if (Subtarget.
hasQPX()) {
6154 if (Flags.isInConsecutiveRegsLast())
6169 NumBytes = std::max(NumBytes, LinkageSize + 8 *
PtrByteSize);
6171 NumBytes = LinkageSize;
6198 Chain = EmitTailCallLoadFPAndRetAddr(DAG,
SPDiff, Chain,
LROp,
FPOp, dl);
6215 for (
unsigned i = 0;
i !=
NumOps; ++
i) {
6218 EVT ArgVT = Outs[
i].VT;
6257 if (Flags.isByVal()) {
6263 unsigned Size = Flags.getByValSize();
6289 if (!isLittleEndian) {
6329 if (!isLittleEndian) {
6367 switch (
Arg.getSimpleValueType().SimpleTy) {
6372 if (Flags.isNest()) {
6388 "Parameter area must exist to pass an argument in memory.");
6433 }
else if (!Flags.isInConsecutiveRegs()) {
6443 if (!isLittleEndian)
6448 }
else if (Flags.isInConsecutiveRegsLast()) {
6451 if (!isLittleEndian)
6469 !isLittleEndian && !Flags.isInConsecutiveRegs()) {
6475 "Parameter area must exist to pass an argument in memory.");
6487 Flags.isInConsecutiveRegs()) ? 4 : 8;
6488 if (Flags.isInConsecutiveRegsLast())
6501 if (!Subtarget.
hasQPX()) {
6512 "Parameter area must exist if we have a varargs call.");
6546 "Parameter area must exist to pass an argument in memory.");
6560 "Invalid QPX parameter type");
6568 "Parameter area must exist if we have a varargs call.");
6602 "Parameter area must exist to pass an argument in memory.");
6618 "mismatch in size of parameter area");
6631 assert(!
CFlags.IsTailCall &&
"Indirect tails calls not supported");
6646 if (isELFv2ABI && !
CFlags.IsPatchPoint)
6667SDValue PPCTargetLowering::LowerCall_Darwin(
6674 unsigned NumOps = Outs.size();
6695 unsigned NumBytes = LinkageSize;
6704 for (
unsigned i = 0;
i !=
NumOps; ++
i) {
6706 EVT ArgVT = Outs[
i].VT;
6711 if (!
CFlags.IsVarArg && !isPPC64) {
6718 NumBytes = ((NumBytes+15)/16)*16;
6725 NumBytes = ((NumBytes+15)/16)*16;
6734 NumBytes = std::max(NumBytes, LinkageSize + 8 *
PtrByteSize);
6758 Chain = EmitTailCallLoadFPAndRetAddr(DAG,
SPDiff, Chain,
LROp,
FPOp, dl);
6777 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
6778 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
6781 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
6782 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
6785 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
6786 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
6798 for (
unsigned i = 0;
i !=
NumOps; ++
i) {
6820 if (Flags.isByVal()) {
6821 unsigned Size = Flags.getByValSize();
6871 switch (
Arg.getSimpleValueType().SimpleTy) {
6999 for (
unsigned i = 0;
i !=
NumOps; ++
i) {
7001 EVT ArgType = Outs[
i].VT;
7023 assert(!
CFlags.IsTailCall &&
"Indirect tail-calls not supported.");
7024 RegsToPass.push_back(std::make_pair((
unsigned)(isPPC64 ? PPC::X12 :
7050 State.getMachineFunction().getSubtarget());
7051 const bool IsPPC64 = Subtarget.
isPPC64();
7057 "Integer argument exceeds register size: should have been legalized");
7069 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
7070 PPC::R7, PPC::R8, PPC::R9, PPC::R10};
7072 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
7073 PPC::X7, PPC::X8, PPC::X9, PPC::X10};
7078 "register width are not supported.");
7080 const unsigned ByValSize =
ArgFlags.getByValSize();
7084 if (ByValSize == 0) {
7086 State.getNextStackOffset(), RegVT,
7092 unsigned Offset = State.AllocateStack(StackSize,
PtrAlign);
7093 for (
const unsigned E = Offset + StackSize; Offset <
E;
7095 if (
unsigned Reg = State.AllocateReg(IsPPC64 ?
GPR_64 :
GPR_32))
7113 assert(IsPPC64 &&
"PPC32 should have split i64 values.");
7122 if (
unsigned Reg = State.AllocateReg(IsPPC64 ?
GPR_64 :
GPR_32))
7135 const unsigned Offset =
7136 State.AllocateStack(IsPPC64 ? 8 : StoreSize,
Align(4));
7137 unsigned FReg = State.AllocateReg(
FPR);
7142 for (
unsigned I = 0;
I < StoreSize;
I +=
PtrAlign.value()) {
7143 if (
unsigned Reg = State.AllocateReg(IsPPC64 ?
GPR_64 :
GPR_32)) {
7144 assert(FReg &&
"An FPR should be available when a GPR is reserved.");
7145 if (State.isVarArg()) {
7177 "i64 should have been split for 32-bit codegen.");
7185 return IsPPC64 ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
7187 return &PPC::F4RCRegClass;
7189 return &PPC::F8RCRegClass;
7202 else if (Flags.isZExt())
7210 const unsigned LASize =
FL->getLinkageSize();
7212 if (PPC::GPRCRegClass.
contains(Reg)) {
7213 assert(Reg >= PPC::R3 && Reg <= PPC::R10 &&
7214 "Reg must be a valid argument register!");
7215 return LASize + 4 * (Reg - PPC::R3);
7218 if (PPC::G8RCRegClass.
contains(Reg)) {
7219 assert(Reg >= PPC::X3 && Reg <= PPC::X10 &&
7220 "Reg must be a valid argument register!");
7221 return LASize + 8 * (Reg - PPC::X3);
7267SDValue PPCTargetLowering::LowerFormalArguments_AIX(
7274 "Unexpected calling convention!");
7287 const bool IsPPC64 = Subtarget.
isPPC64();
7300 CCInfo.AnalyzeFormalArguments(Ins,
CC_AIX);
7304 for (
size_t I = 0, End =
ArgLocs.size();
I != End; ) {
7306 MVT LocVT =
VA.getLocVT();
7315 if (
VA.isMemLoc() &&
VA.needsCustom())
7318 if (Flags.isByVal() &&
VA.isMemLoc()) {
7319 const unsigned Size =
7323 Size,
VA.getLocMemOffset(),
false,
7326 InVals.push_back(
FIN);
7331 if (Flags.isByVal()) {
7332 assert(
VA.isRegLoc() &&
"MemLocs should already be handled.");
7345 InVals.push_back(
FIN);
7349 IsPPC64 ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
7353 const unsigned VReg = MF.
addLiveIn(PhysReg, RegClass);
7377 "RegLocs should be for ByVal argument.");
7383 if (Offset != StackSize) {
7385 "Expected MemLoc for remaining bytes.");
7386 assert(
ArgLocs[
I].isMemLoc() &&
"Expected MemLoc for remaining bytes.");
7395 EVT ValVT =
VA.getValVT();
7396 if (
VA.isRegLoc() && !
VA.needsCustom()) {
7406 InVals.push_back(ArgValue);
7409 if (
VA.isMemLoc()) {
7413 "Object size is larger than size of MemLoc");
7419 const bool IsImmutable =
7426 InVals.push_back(ArgValue);
7451 static const MCPhysReg GPR_32[] = {PPC::R3, PPC::R4, PPC::R5, PPC::R6,
7452 PPC::R7, PPC::R8, PPC::R9, PPC::R10};
7454 static const MCPhysReg GPR_64[] = {PPC::X3, PPC::X4, PPC::X5, PPC::X6,
7455 PPC::X7, PPC::X8, PPC::X9, PPC::X10};
7462 (CCInfo.getNextStackOffset() - LinkageSize) /
PtrByteSize;
7465 const unsigned VReg =
7485SDValue PPCTargetLowering::LowerCall_AIX(
7498 "Unexpected calling convention!");
7520 const bool IsPPC64 = Subtarget.
isPPC64();
7524 CCInfo.AnalyzeCallOperands(Outs,
CC_AIX);
7534 CCInfo.getNextStackOffset());
7550 for (
unsigned I = 0,
E =
ArgLocs.size();
I !=
E;) {
7551 const unsigned ValNo =
ArgLocs[
I].getValNo();
7555 if (Flags.isByVal()) {
7556 const unsigned ByValSize = Flags.getByValSize();
7581 "Unexpected location for pass-by-value argument.");
7590 "Expected additional location for by-value argument.");
7613 "Unexpected register residue for by-value argument.");
7628 assert(
PtrVT.getSimpleVT().getSizeInBits() > (Bytes * 8) &&
7629 "Unexpected load emitted during handling of pass-by-value "
7631 unsigned NumSHLBits =
PtrVT.getSimpleVT().getSizeInBits() - (Bytes * 8);
7648 const MVT LocVT =
VA.getLocVT();
7649 const MVT ValVT =
VA.getValVT();
7651 switch (
VA.getLocInfo()) {
7664 if (
VA.isRegLoc() && !
VA.needsCustom()) {
7669 if (
VA.isMemLoc()) {
7683 "Unexpected register handling for calling convention.");
7700 "Unexpected custom register for argument!");
7712 assert(
PeekArg.needsCustom() &&
"A second custom GPR is expected.");
7727 assert(!
CFlags.IsTailCall &&
"Indirect tail-calls not supported.");
7731 const unsigned TOCSaveOffset =
7764 return CCInfo.CheckReturn(
7779 CCInfo.AnalyzeReturn(Outs,
7790 assert(
VA.isRegLoc() &&
"Can only return in registers!");
7794 switch (
VA.getLocInfo()) {
7836PPCTargetLowering::LowerGET_DYNAMIC_AREA_OFFSET(
SDValue Op,
7861 bool isPPC64 = Subtarget.
isPPC64();
7862 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1;
7882 bool isPPC64 = Subtarget.
isPPC64();
7903PPCTargetLowering::getFramePointerFrameIndex(
SelectionDAG & DAG)
const {
7905 bool isPPC64 = Subtarget.
isPPC64();
7951 bool isPPC64 = Subtarget.
isPPC64();
7963 Op.getOperand(0),
Op.getOperand(1));
7970 Op.getOperand(0),
Op.getOperand(1));
7974 if (
Op.getValueType().isVector())
7975 return LowerVectorLoad(Op, DAG);
7978 "Custom lowering only for i1 loads");
7999 if (
Op.getOperand(1).getValueType().isVector())
8000 return LowerVectorStore(Op, DAG);
8003 "Custom lowering only for i1 stores");
8023 "Custom lowering only for i1 results");
8051 assert(
Op.getValueType().isVector() &&
"Vector type expected.");
8055 unsigned SrcSize =
N1.getValueType().getSizeInBits();
8056 assert(
SrcSize <= 128 &&
"Source must fit in an Altivec/VSX vector");
8088 if (!
Op.getOperand(0).getValueType().isFloatingPoint() ||
8089 !
Op.getOperand(2).getValueType().isFloatingPoint())
8096 SDValue LHS =
Op.getOperand(0), RHS =
Op.getOperand(1);
8205void PPCTargetLowering::LowerFP_TO_INTForReuse(
SDValue Op, ReuseLoadInfo &
RLI,
8207 const SDLoc &dl)
const {
8208 assert(
Op.getOperand(0).getValueType().isFloatingPoint());
8214 switch (
Op.getSimpleValueType().SimpleTy) {
8220 : (Subtarget.hasFPCVT() ? PPCISD::
FCTIWUZ : PPCISD::
FCTIDZ),
8225 "i64 FP_TO_UINT is supported only with FPCVT");
8245 Alignment =
Align(4);
8265 RLI.Alignment = Alignment;
8273 const SDLoc &dl)
const {
8274 assert(
Op.getOperand(0).getValueType().isFloatingPoint());
8281 switch (
Op.getSimpleValueType().SimpleTy) {
8287 : (Subtarget.hasFPCVT() ? PPCISD::
FCTIWUZ : PPCISD::
FCTIDZ),
8293 "i64 FP_TO_UINT is supported only with FPCVT");
8304 const SDLoc &dl)
const {
8307 if (
Op->getOperand(0).getValueType() ==
MVT::f128)
8329 const uint64_t
TwoE31[] = {0x41e0000000000000LL, 0};
8336 Op.getOperand(0), Tmp);
8342 return DAG.
getSelectCC(dl,
Op.getOperand(0), Tmp, True, False,
8351 return LowerFP_TO_INTDirectMove(Op, DAG, dl);
8354 LowerFP_TO_INTForReuse(Op,
RLI, DAG, dl);
8357 RLI.Alignment,
RLI.MMOFlags(),
RLI.AAInfo,
RLI.Ranges);
8378 Op.getOperand(0).getValueType())) {
8380 LowerFP_TO_INTForReuse(Op,
RLI, DAG, dl);
8385 if (!LD ||
LD->getExtensionType() !=
ET ||
LD->isVolatile() ||
8386 LD->isNonTemporal())
8388 if (
LD->getMemoryVT() !=
MemVT)
8391 RLI.Ptr =
LD->getBasePtr();
8392 if (
LD->isIndexed() && !
LD->getOffset().isUndef()) {
8394 "Non-pre-inc AM on PPC?");
8399 RLI.Chain =
LD->getChain();
8400 RLI.MPI =
LD->getPointerInfo();
8401 RLI.IsDereferenceable =
LD->isDereferenceable();
8402 RLI.IsInvariant =
LD->isInvariant();
8403 RLI.Alignment =
LD->getAlign();
8404 RLI.AAInfo =
LD->getAAInfo();
8405 RLI.Ranges =
LD->getRanges();
8415void PPCTargetLowering::spliceIntoChain(
SDValue ResChain,
8426 "A new TF really is required here");
8435bool PPCTargetLowering::directMoveIsProfitable(
const SDValue &Op)
const {
8436 SDNode *Origin =
Op.getOperand(0).getNode();
8451 if (UI.getUse().get().getResNo() != 0)
8467 const SDLoc &dl)
const {
8470 "Invalid floating point type as target of conversion");
8472 "Int to FP conversions with direct moves require FPCVT");
8515 const SDLoc &dl)
const {
8517 unsigned Opc =
Op.getOpcode();
8519 "Unexpected conversion type");
8521 "Supports conversions to v2f64/v4f32 only.");
8568 EVT InVT =
Op.getOperand(0).getValueType();
8570 if (
OutVT.isVector() &&
OutVT.isFloatingPoint() &&
8572 return LowerINT_TO_FPVector(Op, DAG, dl);
8603 if (
Op.getOperand(0).getValueType() ==
MVT::i1)
8610 if (Subtarget.
hasDirectMove() && directMoveIsProfitable(Op) &&
8612 return LowerINT_TO_FPDirectMove(Op, DAG, dl);
8615 "UINT_TO_FP is supported only with FPCVT");
8628 if (
Op.getOperand(0).getValueType() ==
MVT::i64) {
8684 RLI.Alignment,
RLI.MMOFlags(),
RLI.AAInfo,
RLI.Ranges);
8685 spliceIntoChain(
RLI.ResChain,
Bits.getValue(1), DAG);
8695 spliceIntoChain(
RLI.ResChain,
Bits.getValue(1), DAG);
8705 spliceIntoChain(
RLI.ResChain,
Bits.getValue(1), DAG);
8723 "Expected an i32 store");
8738 Ops,
MVT::i32, MMO);
8751 "Unhandled INT_TO_FP type in custom expander!");
8775 "Expected an i32 store");
8791 Ops,
MVT::i32, MMO);
8793 spliceIntoChain(
RLI.ResChain,
Ld.getValue(1), DAG);
8796 "i32->FP without LFIWAX supported only on PPC64");
8846 EVT VT =
Op.getValueType();
8852 Chain =
MFFS.getValue(1);
8863 Chain =
CWD.getValue(1);
8888 EVT VT =
Op.getValueType();
8892 VT ==
Op.getOperand(1).getValueType() &&
8917 EVT VT =
Op.getValueType();
8921 VT ==
Op.getOperand(1).getValueType() &&
8947 EVT VT =
Op.getValueType();
8950 VT ==
Op.getOperand(1).getValueType() &&
8989 if (Val == ((1LU << (
SplatSize * 8)) - 1)) {
9038 for (
unsigned i = 0;
i != 16; ++
i)
9059 EVT VecVT = V->getValueType(0);
9066 bool IsSplat =
true;
9067 bool IsLoad =
false;
9073 if (V->isConstant())
9075 for (
int i = 0, e = V->getNumOperands();
i < e; ++
i) {
9076 if (V->getOperand(
i).isUndef())
9080 if (V->getOperand(
i).getOpcode() ==
ISD::LOAD ||
9082 V->getOperand(
i).getOperand(0).getOpcode() ==
ISD::LOAD) ||
9084 V->getOperand(
i).getOperand(0).getOpcode() ==
ISD::LOAD) ||
9086 V->getOperand(
i).getOperand(0).getOpcode() ==
ISD::LOAD))
9090 if (V->getOperand(
i) != Op0 ||
9091 (!IsLoad && !V->isOnlyUserOf(V->getOperand(
i).getNode())))
9094 return !(IsSplat && IsLoad);
9165 assert(
BVN &&
"Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
9179 "BUILD_VECTOR for v4i1 does not have 4 operands");
9181 bool IsConst =
true;
9182 for (
unsigned i = 0;
i < 4; ++
i) {
9183 if (
BVN->getOperand(
i).isUndef())
continue;
9197 for (
unsigned i = 0;
i < 4; ++
i) {
9198 if (
BVN->getOperand(
i).isUndef())
9218 for (
unsigned i = 0;
i < 4; ++
i) {
9219 if (
BVN->getOperand(
i).isUndef())
continue;
9225 unsigned StoreSize =
BVN->getOperand(
i).getValueType().getStoreSize();
9226 if (StoreSize > 4) {
9241 if (!Stores.empty())
9273 unsigned SplatBitSize;
9283 (SplatBitSize == 64) && (
Op->getValueType(0) ==
MVT::v2f64) &&
9302 unsigned ElementSize =
LD->getMemoryVT().getScalarSizeInBits();
9307 if (
InputLoad->getNode()->hasNUsesOfValue(128 / ElementSize, 0) &&
9308 ((Subtarget.
hasVSX() && ElementSize == 64) ||
9309 (Subtarget.
hasP9Vector() && ElementSize == 32))) {
9318 Ops,
LD->getMemoryVT(),
LD->getMemOperand());
9325 if (Subtarget.
hasVSX() &&
9339 if (SplatBits == 0) {
9355 Op.getValueType(), DAG, dl);
9367 int32_t
SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
9391 if (VT ==
Op.getValueType())
9400 if (
SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
9414 static const signed char SplatCsts[] = {
9415 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
9416 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
9431 static const unsigned IIDs[] = {
9432 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
9433 Intrinsic::ppc_altivec_vslw
9442 static const unsigned IIDs[] = {
9443 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
9444 Intrinsic::ppc_altivec_vsrw
9453 static const unsigned IIDs[] = {
9454 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
9455 Intrinsic::ppc_altivec_vsraw
9465 static const unsigned IIDs[] = {
9466 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
9467 Intrinsic::ppc_altivec_vrlw
9474 if (
SextVal == (
int)(((
unsigned)
i << 8) | (
i < 0 ? 0xFF : 0))) {
9480 if (
SextVal == (
int)(((
unsigned)
i << 16) | (
i < 0 ? 0xFFFF : 0))) {
9486 if (
SextVal == (
int)(((
unsigned)
i << 24) | (
i < 0 ? 0xFFFFFF : 0))) {
9501 unsigned OpNum = (
PFEntry >> 26) & 0x0F;
9519 if (
LHSID == (1*9+2)*9+3)
return LHS;
9520 assert(
LHSID == ((4*9+5)*9+6)*9+7 &&
"Illegal OP_COPY!");
9544 for (
unsigned i = 0;
i != 16; ++
i)
9548 for (
unsigned i = 0;
i != 16; ++
i)
9552 for (
unsigned i = 0;
i != 16; ++
i)
9556 for (
unsigned i = 0;
i != 16; ++
i)
9588 0, 15, 14, 13, 12, 11, 10, 9};
9590 1, 2, 3, 4, 5, 6, 7, 8};
9593 int OriginalOrder[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15};
9796 auto ShuffleMask =
SVN->getMask();
9818 unsigned SplatBitSize;
9834 if ((ShuffleMask[0] == 0 && ShuffleMask[8] == 8) &&
9835 (ShuffleMask[4] % 4 == 0 && ShuffleMask[12] % 4 == 0 &&
9836 ShuffleMask[4] > 15 && ShuffleMask[12] > 15))
9838 else if ((ShuffleMask[4] == 4 && ShuffleMask[12] == 12) &&
9839 (ShuffleMask[0] % 4 == 0 && ShuffleMask[8] % 4 == 0 &&
9840 ShuffleMask[0] > 15 && ShuffleMask[8] > 15))
9848 for (; SplatBitSize < 32; SplatBitSize <<= 1)
9864 "Only set v1i128 as custom, other type shouldn't reach here!");
9868 unsigned SHLAmt =
N1.getConstantOperandVal(0);
9871 std::iota(
Mask.begin(),
Mask.end(), 0);
9906 V1 =
Op.getOperand(0);
9907 V2 =
Op.getOperand(1);
9909 EVT VT =
Op.getValueType();
9931 assert(isLittleEndian &&
"Unexpected permuted load on big endian target");
9934 "Splat of a value outside of the loaded memory");
9959 Ops,
LD->getMemoryVT(),
LD->getMemOperand());
9960 if (
LdSplt.getValueType() !=
SVOp->getValueType(0))
9999 if (Subtarget.
hasVSX() &&
10012 if (Subtarget.
hasVSX() &&
10045 if (Subtarget.
hasVSX()) {
10063 if (Subtarget.
hasQPX()) {
10067 if (
V2.isUndef())
V2 =
V1;
10073 }
else if (
SVOp->isSplat()) {
10088 for (
unsigned i = 0;
i < 4; ++
i) {
10089 int m =
SVOp->getMaskElt(
i);
10091 idx |=
mm << (3-
i)*3;
10102 if (
V2.isUndef()) {
10126 unsigned int ShuffleKind = isLittleEndian ? 2 : 0;
10149 unsigned EltNo = 8;
10150 for (
unsigned j = 0;
j != 4; ++
j) {
10181 unsigned Cost = (
PFEntry >> 30);
10200 if (
V2.isUndef())
V2 =
V1;
10209 EVT EltVT =
V1.getValueType().getVectorElementType();
10217 if (isLittleEndian)
10227 LLVM_DEBUG(
dbgs() <<
"Emitting a VPERM for the following shuffle:\n");
10229 LLVM_DEBUG(
dbgs() <<
"With the following permute control vector:\n");
10232 if (isLittleEndian)
10245 unsigned IntrinsicID =
10249 switch (IntrinsicID) {
10253 case Intrinsic::ppc_altivec_vcmpbfp_p:
10257 case Intrinsic::ppc_altivec_vcmpeqfp_p:
10261 case Intrinsic::ppc_altivec_vcmpequb_p:
10265 case Intrinsic::ppc_altivec_vcmpequh_p:
10269 case Intrinsic::ppc_altivec_vcmpequw_p:
10273 case Intrinsic::ppc_altivec_vcmpequd_p:
10280 case Intrinsic::ppc_altivec_vcmpneb_p:
10281 case Intrinsic::ppc_altivec_vcmpneh_p:
10282 case Intrinsic::ppc_altivec_vcmpnew_p:
10283 case Intrinsic::ppc_altivec_vcmpnezb_p:
10284 case Intrinsic::ppc_altivec_vcmpnezh_p:
10285 case Intrinsic::ppc_altivec_vcmpnezw_p:
10287 switch (IntrinsicID) {
10290 case Intrinsic::ppc_altivec_vcmpneb_p:
10293 case Intrinsic::ppc_altivec_vcmpneh_p:
10296 case Intrinsic::ppc_altivec_vcmpnew_p:
10299 case Intrinsic::ppc_altivec_vcmpnezb_p:
10302 case Intrinsic::ppc_altivec_vcmpnezh_p:
10305 case Intrinsic::ppc_altivec_vcmpnezw_p:
10313 case Intrinsic::ppc_altivec_vcmpgefp_p:
10317 case Intrinsic::ppc_altivec_vcmpgtfp_p:
10321 case Intrinsic::ppc_altivec_vcmpgtsb_p:
10325 case Intrinsic::ppc_altivec_vcmpgtsh_p:
10329 case Intrinsic::ppc_altivec_vcmpgtsw_p:
10333 case Intrinsic::ppc_altivec_vcmpgtsd_p:
10340 case Intrinsic::ppc_altivec_vcmpgtub_p:
10344 case Intrinsic::ppc_altivec_vcmpgtuh_p:
10348 case Intrinsic::ppc_altivec_vcmpgtuw_p:
10352 case Intrinsic::ppc_altivec_vcmpgtud_p:
10361 case Intrinsic::ppc_vsx_xvcmpeqdp_p:
10362 case Intrinsic::ppc_vsx_xvcmpgedp_p:
10363 case Intrinsic::ppc_vsx_xvcmpgtdp_p:
10364 case Intrinsic::ppc_vsx_xvcmpeqsp_p:
10365 case Intrinsic::ppc_vsx_xvcmpgesp_p:
10366 case Intrinsic::ppc_vsx_xvcmpgtsp_p:
10367 if (Subtarget.
hasVSX()) {
10368 switch (IntrinsicID) {
10369 case Intrinsic::ppc_vsx_xvcmpeqdp_p:
10372 case Intrinsic::ppc_vsx_xvcmpgedp_p:
10375 case Intrinsic::ppc_vsx_xvcmpgtdp_p:
10378 case Intrinsic::ppc_vsx_xvcmpeqsp_p:
10381 case Intrinsic::ppc_vsx_xvcmpgesp_p:
10384 case Intrinsic::ppc_vsx_xvcmpgtsp_p:
10394 case Intrinsic::ppc_altivec_vcmpbfp:
10397 case Intrinsic::ppc_altivec_vcmpeqfp:
10400 case Intrinsic::ppc_altivec_vcmpequb:
10403 case Intrinsic::ppc_altivec_vcmpequh:
10406 case Intrinsic::ppc_altivec_vcmpequw:
10409 case Intrinsic::ppc_altivec_vcmpequd:
10415 case Intrinsic::ppc_altivec_vcmpneb:
10416 case Intrinsic::ppc_altivec_vcmpneh:
10417 case Intrinsic::ppc_altivec_vcmpnew:
10418 case Intrinsic::ppc_altivec_vcmpnezb:
10419 case Intrinsic::ppc_altivec_vcmpnezh:
10420 case Intrinsic::ppc_altivec_vcmpnezw:
10422 switch (IntrinsicID) {
10425 case Intrinsic::ppc_altivec_vcmpneb:
10428 case Intrinsic::ppc_altivec_vcmpneh:
10431 case Intrinsic::ppc_altivec_vcmpnew:
10434 case Intrinsic::ppc_altivec_vcmpnezb:
10437 case Intrinsic::ppc_altivec_vcmpnezh:
10440 case Intrinsic::ppc_altivec_vcmpnezw:
10447 case Intrinsic::ppc_altivec_vcmpgefp:
10450 case Intrinsic::ppc_altivec_vcmpgtfp:
10453 case Intrinsic::ppc_altivec_vcmpgtsb:
10456 case Intrinsic::ppc_altivec_vcmpgtsh:
10459 case Intrinsic::ppc_altivec_vcmpgtsw:
10462 case Intrinsic::ppc_altivec_vcmpgtsd:
10468 case Intrinsic::ppc_altivec_vcmpgtub:
10471 case Intrinsic::ppc_altivec_vcmpgtuh:
10474 case Intrinsic::ppc_altivec_vcmpgtuw:
10477 case Intrinsic::ppc_altivec_vcmpgtud:
10491 unsigned IntrinsicID =
10496 if (IntrinsicID == Intrinsic::thread_pointer) {
10513 Op.getOperand(1),
Op.getOperand(2),
10573 case Intrinsic::ppc_cfence: {
10574 assert(
ArgStart == 1 &&
"llvm.ppc.cfence must carry a chain argument.");
10575 assert(Subtarget.
isPPC64() &&
"Only 64-bit is supported for now.");
10597 int VectorIndex = 0;
10610 "Expecting an atomic compare-and-swap here.");
10614 if (
MemVT.getSizeInBits() >= 32)
10660 "Should only be called for ISD::INSERT_VECTOR_ELT");
10667 EVT VT =
Op.getValueType();
10692 "Unknown extract_vector_elt type");
10756 unsigned Alignment =
LN->getAlignment();
10759 if (Alignment >=
MemVT.getStoreSize())
10767 for (
unsigned Idx = 0;
Idx < 4; ++
Idx) {
10772 LN->getPointerInfo().getWithOffset(
Idx * Stride),
10774 LN->getMemOperand()->getFlags(),
LN->getAAInfo());
10777 LN->getPointerInfo().getWithOffset(
Idx * Stride),
10779 LN->getMemOperand()->getFlags(),
LN->getAAInfo());
10781 if (
Idx == 0 &&
LN->isIndexed()) {
10783 "Unknown addressing mode on vector load");
10785 LN->getAddressingMode());
10799 if (
LN->isIndexed()) {
10809 assert(
LN->isUnindexed() &&
"Indexed v4i1 loads are not supported");
10815 for (
unsigned i = 0;
i < 4; ++
i) {
10821 LN->getPointerInfo().getWithOffset(
i),
MVT::i8,
10822 1,
LN->getMemOperand()->getFlags(),
LN->getAAInfo());
10845 unsigned Alignment =
SN->getAlignment();
10848 if (Alignment >=
MemVT.getStoreSize())
10856 for (
unsigned Idx = 0;
Idx < 4; ++
Idx) {
10863 SN->getPointerInfo().getWithOffset(
Idx * Stride),
10865 SN->getMemOperand()->getFlags(),
SN->getAAInfo());
10868 SN->getPointerInfo().getWithOffset(
Idx * Stride),
10870 SN->getMemOperand()->getFlags(),
SN->getAAInfo());
10872 if (
Idx == 0 &&
SN->isIndexed()) {
10874 "Unknown addressing mode on vector store");
10876 SN->getAddressingMode());
10887 if (
SN->isIndexed()) {
10895 assert(
SN->isUnindexed() &&
"Indexed v4i1 stores are not supported");
10931 for (
unsigned i = 0;
i < 4; ++
i) {
10944 for (
unsigned i = 0;
i < 4; ++
i) {
10950 MVT::i8, 1,
SN->getMemOperand()->getFlags(),
10962 SDValue LHS =
Op.getOperand(0), RHS =
Op.getOperand(1);
10987 SDValue LHS =
Op.getOperand(0), RHS =
Op.getOperand(1);
11005 for (
unsigned i = 0;
i != 8; ++
i) {
11006 if (isLittleEndian) {
11008 Ops[
i*2+1] = 2*
i+16;
11011 Ops[
i*2+1] = 2*
i+1+16;
11014 if (isLittleEndian)
11025 assert(
Op.getOpcode() ==
ISD::ABS &&
"Should only be called for ISD::ABS");
11027 EVT VT =
Op.getValueType();
11029 "Only set vector abs as custom, scalar abs shouldn't reach here!");
11032 "Unexpected vector element type!");
11034 "Current subtarget doesn't support smax v2i64!");
11052 BifID = Intrinsic::ppc_altivec_vmaxsd;
11054 BifID = Intrinsic::ppc_altivec_vmaxsh;
11056 BifID = Intrinsic::ppc_altivec_vmaxsb;
11065 "Should only be called for ISD::FP_EXTEND");
11082 "Node should have 2 operands with second one being a constant!");
11117 LD->getMemoryVT(),
LD->getMemOperand());
11130 LD->getMemoryVT(),
LD->getMemOperand());
11141 switch (Op.getOpcode()) {
11148 case ISD::SETCC:
return LowerSETCC(Op, DAG);
11154 case ISD::VAARG:
return LowerVAARG(Op, DAG);
11160 return LowerGET_DYNAMIC_AREA_OFFSET(Op, DAG);
11167 case ISD::LOAD:
return LowerLOAD(Op, DAG);
11168 case ISD::STORE:
return LowerSTORE(Op, DAG);
11189 case ISD::MUL:
return LowerMUL(Op, DAG);
11190 case ISD::ABS:
return LowerABS(Op, DAG);
11192 case ISD::ROTL:
return LowerROTL(Op, DAG);
11204 return LowerINTRINSIC_VOID(Op, DAG);
11206 return LowerBSWAP(Op, DAG);
11208 return LowerATOMIC_CMP_SWAP(Op, DAG);
11216 switch (
N->getOpcode()) {
11218 llvm_unreachable(
"Do not know how to custom type legalize this operation!");
11230 Intrinsic::loop_decrement)
11234 "Unexpected result type for CTR decrement intrinsic");
11236 N->getValueType(0));
11249 EVT VT =
N->getValueType(0);
11268 EVT OpVT =
N->getOperand(0).getValueType();
11269 if (
TrgVT.isVector() &&
11271 OpVT.getSizeInBits() <= 128 &&
11292 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
11294 return Builder.CreateCall(Func, {});
11317 return Builder.CreateCall(
11319 Builder.GetInsertBlock()->getParent()->getParent(),
11320 Intrinsic::ppc_cfence, {Inst->getType()}),
11382 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
11386 RegInfo.createVirtualRegister(
AtomicSize == 8 ? &PPC::G8RCRegClass
11387 : &PPC::GPRCRegClass);
11419 Register ExtReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
11462 bool is64bit = Subtarget.
isPPC64();
11464 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
11486 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
11490 is64bit ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
11496 isLittleEndian ?
Shift1Reg : RegInfo.createVirtualRegister(
GPRC);
11534 Ptr1Reg = RegInfo.createVirtualRegister(RC);
11548 if (!isLittleEndian)
11549 BuildMI(BB, dl,
TII->get(PPC::XORI), ShiftReg)
11653 Register DstReg =
MI.getOperand(0).getReg();
11661 "Invalid Pointer Size!");
11689 sinkMBB->transferSuccessorsAndUpdatePHIs(
MBB);
11725 BaseReg = Subtarget.
isPPC64() ? PPC::X1 : PPC::R1;
11727 BaseReg = Subtarget.
isPPC64() ? PPC::BP8 : PPC::BP;
11730 TII->get(Subtarget.
isPPC64() ? PPC::STD : PPC::STW))
11774 TII->get(PPC::PHI), DstReg)
11778 MI.eraseFromParent();
11793 "Invalid Pointer Size!");
11796 (
PVT ==
MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
11800 unsigned SP = (
PVT ==
MVT::i64) ? PPC::X1 : PPC::R1;
11810 const int64_t SPOffset = 2 *
PVT.getStoreSize();
11880 MI.eraseFromParent();
11896 "Unexpected stack alignment");
11899 unsigned StackProbeSize = 4096;
11906 StackProbeSize &= ~(StackAlign - 1);
11907 return StackProbeSize ? StackProbeSize : StackAlign;
11919 const bool isPPC64 = Subtarget.
isPPC64();
11958 Register DstReg =
MI.getOperand(0).getReg();
11960 Register SPReg = isPPC64 ? PPC::X1 : PPC::R1;
11971 isPPC64 ? PPC::PREPARE_PROBED_ALLOCA_64 : PPC::PREPARE_PROBED_ALLOCA_32;
11977 ProbeOpc = isPPC64 ? PPC::PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64
11978 : PPC::PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_32;
11982 .
add(
MI.getOperand(2))
11983 .
add(
MI.getOperand(3));
12055 MRI.createVirtualRegister(isPPC64 ?
G8RC :
GPRC);
12057 TII->get(isPPC64 ? PPC::DYNAREAOFFSET8 : PPC::DYNAREAOFFSET),
12059 .
add(
MI.getOperand(2))
12060 .add(
MI.getOperand(3));
12068 TailMBB->transferSuccessorsAndUpdatePHIs(
MBB);
12072 MI.eraseFromParent();
12081 if (
MI.getOpcode() == TargetOpcode::STACKMAP ||
12082 MI.getOpcode() == TargetOpcode::PATCHPOINT) {
12084 MI.getOpcode() == TargetOpcode::PATCHPOINT &&
12097 if (
MI.getOpcode() == PPC::EH_SjLj_SetJmp32 ||
12098 MI.getOpcode() == PPC::EH_SjLj_SetJmp64) {
12100 }
else if (
MI.getOpcode() == PPC::EH_SjLj_LongJmp32 ||
12101 MI.getOpcode() == PPC::EH_SjLj_LongJmp64) {
12114 if (
MI.getOpcode() == PPC::SELECT_CC_I4 ||
12115 MI.getOpcode() == PPC::SELECT_CC_I8 ||
MI.getOpcode() == PPC::SELECT_I4 ||
12116 MI.getOpcode() == PPC::SELECT_I8) {
12118 if (
MI.getOpcode() == PPC::SELECT_CC_I4 ||
12119 MI.getOpcode() == PPC::SELECT_CC_I8)
12120 Cond.push_back(
MI.getOperand(4));
12123 Cond.push_back(
MI.getOperand(1));
12126 TII->insertSelect(*BB,
MI, dl,
MI.getOperand(0).getReg(),
Cond,
12127 MI.getOperand(2).getReg(),
MI.getOperand(3).getReg());
12128 }
else if (
MI.getOpcode() == PPC::SELECT_CC_F4 ||
12129 MI.getOpcode() == PPC::SELECT_CC_F8 ||
12130 MI.getOpcode() == PPC::SELECT_CC_F16 ||
12131 MI.getOpcode() == PPC::SELECT_CC_QFRC ||
12132 MI.getOpcode() == PPC::SELECT_CC_QSRC ||
12133 MI.getOpcode() == PPC::SELECT_CC_QBRC ||
12134 MI.getOpcode() == PPC::SELECT_CC_VRRC ||
12135 MI.getOpcode() == PPC::SELECT_CC_VSFRC ||
12136 MI.getOpcode() == PPC::SELECT_CC_VSSRC ||
12137 MI.getOpcode() == PPC::SELECT_CC_VSRC ||
12138 MI.getOpcode() == PPC::SELECT_CC_SPE4 ||
12139 MI.getOpcode() == PPC::SELECT_CC_SPE ||
12140 MI.getOpcode() == PPC::SELECT_F4 ||
12141 MI.getOpcode() == PPC::SELECT_F8 ||
12142 MI.getOpcode() == PPC::SELECT_F16 ||
12143 MI.getOpcode() == PPC::SELECT_QFRC ||
12144 MI.getOpcode() == PPC::SELECT_QSRC ||
12145 MI.getOpcode() == PPC::SELECT_QBRC ||
12146 MI.getOpcode() == PPC::SELECT_SPE ||
12147 MI.getOpcode() == PPC::SELECT_SPE4 ||
12148 MI.getOpcode() == PPC::SELECT_VRRC ||
12149 MI.getOpcode() == PPC::SELECT_VSFRC ||
12150 MI.getOpcode() == PPC::SELECT_VSSRC ||
12151 MI.getOpcode() == PPC::SELECT_VSRC) {
12172 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
12178 if (
MI.getOpcode() == PPC::SELECT_I4 ||
MI.getOpcode() == PPC::SELECT_I8 ||
12179 MI.getOpcode() == PPC::SELECT_F4 ||
MI.getOpcode() == PPC::SELECT_F8 ||
12180 MI.getOpcode() == PPC::SELECT_F16 ||
12181 MI.getOpcode() == PPC::SELECT_SPE4 ||
12182 MI.getOpcode() == PPC::SELECT_SPE ||
12183 MI.getOpcode() == PPC::SELECT_QFRC ||
12184 MI.getOpcode() == PPC::SELECT_QSRC ||
12185 MI.getOpcode() == PPC::SELECT_QBRC ||
12186 MI.getOpcode() == PPC::SELECT_VRRC ||
12187 MI.getOpcode() == PPC::SELECT_VSFRC ||
12188 MI.getOpcode() == PPC::SELECT_VSSRC ||
12189 MI.getOpcode() == PPC::SELECT_VSRC) {
12191 .
addReg(
MI.getOperand(1).getReg())
12197 .
addReg(
MI.getOperand(1).getReg())
12214 .
addReg(
MI.getOperand(3).getReg())
12216 .
addReg(
MI.getOperand(2).getReg())
12218 }
else if (
MI.getOpcode() == PPC::ReadTB) {
12240 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
12254 Register CmpReg = RegInfo.createVirtualRegister(&PPC::CRRCRegClass);
12266 }
else if (
MI.getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
12268 else if (
MI.getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
12270 else if (
MI.getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
12272 else if (
MI.getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
12275 else if (
MI.getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
12277 else if (
MI.getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
12279 else if (
MI.getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
12281 else if (
MI.getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
12284 else if (
MI.getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
12286 else if (
MI.getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
12288 else if (
MI.getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
12290 else if (
MI.getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
12293 else if (
MI.getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
12295 else if (
MI.getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
12297 else if (
MI.getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
12299 else if (
MI.getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
12302 else if (
MI.getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
12304 else if (
MI.getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
12306 else if (
MI.getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
12308 else if (
MI.getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
12311 else if (
MI.getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
12313 else if (
MI.getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
12315 else if (
MI.getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
12317 else if (
MI.getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
12320 else if (
MI.getOpcode() == PPC::ATOMIC_LOAD_MIN_I8)
12322 else if (
MI.getOpcode() == PPC::ATOMIC_LOAD_MIN_I16)
12324 else if (
MI.getOpcode() == PPC::ATOMIC_LOAD_MIN_I32)
12326 else if (
MI.getOpcode() == PPC::ATOMIC_LOAD_MIN_I64)
12329 else if (
MI.getOpcode() == PPC::ATOMIC_LOAD_MAX_I8)
12331 else if (
MI.getOpcode() == PPC::ATOMIC_LOAD_MAX_I16)
12333 else if (
MI.getOpcode() == PPC::ATOMIC_LOAD_MAX_I32)
12335 else if (
MI.getOpcode() == PPC::ATOMIC_LOAD_MAX_I64)
12338 else if (
MI.getOpcode() == PPC::ATOMIC_LOAD_UMIN_I8)
12340 else if (
MI.getOpcode() == PPC::ATOMIC_LOAD_UMIN_I16)
12342 else if (
MI.getOpcode() == PPC::ATOMIC_LOAD_UMIN_I32)
12344 else if (
MI.getOpcode() == PPC::ATOMIC_LOAD_UMIN_I64)
12347 else if (
MI.getOpcode() == PPC::ATOMIC_LOAD_UMAX_I8)
12349 else if (
MI.getOpcode() == PPC::ATOMIC_LOAD_UMAX_I16)
12351 else if (
MI.getOpcode() == PPC::ATOMIC_LOAD_UMAX_I32)
12353 else if (
MI.getOpcode() == PPC::ATOMIC_LOAD_UMAX_I64)
12356 else if (
MI.getOpcode() == PPC::ATOMIC_SWAP_I8)
12358 else if (
MI.getOpcode() == PPC::ATOMIC_SWAP_I16)
12360 else if (
MI.getOpcode() == PPC::ATOMIC_SWAP_I32)
12362 else if (
MI.getOpcode() == PPC::ATOMIC_SWAP_I64)
12364 else if (
MI.getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
12365 MI.getOpcode() == PPC::ATOMIC_CMP_SWAP_I64 ||
12367 MI.getOpcode() == PPC::ATOMIC_CMP_SWAP_I8) ||
12369 MI.getOpcode() == PPC::ATOMIC_CMP_SWAP_I16)) {
12370 bool is64bit =
MI.getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
12374 switch (
MI.getOpcode()) {
12377 case PPC::ATOMIC_CMP_SWAP_I8:
12382 case PPC::ATOMIC_CMP_SWAP_I16:
12387 case PPC::ATOMIC_CMP_SWAP_I32:
12391 case PPC::ATOMIC_CMP_SWAP_I64:
12413 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
12433 BuildMI(BB, dl,
TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
12466 }
else if (
MI.getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
12467 MI.getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
12471 bool is64bit = Subtarget.
isPPC64();
12473 bool is8bit =
MI.getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
12492 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
12496 is64bit ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
12502 isLittleEndian ?
Shift1Reg : RegInfo.createVirtualRegister(
GPRC);
12514 Register TmpReg = RegInfo.createVirtualRegister(
GPRC);
12549 Ptr1Reg = RegInfo.createVirtualRegister(RC);
12564 if (!isLittleEndian)
12565 BuildMI(BB, dl,
TII->get(PPC::XORI), ShiftReg)
12610 BuildMI(BB, dl,
TII->get(PPC::CMPW), PPC::CR0)
12652 }
else if (
MI.getOpcode() == PPC::FADDrtz) {
12662 Register MFFSReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
12676 }
else if (
MI.getOpcode() == PPC::ANDI_rec_1_EQ_BIT ||
12677 MI.getOpcode() == PPC::ANDI_rec_1_GT_BIT ||
12678 MI.getOpcode() == PPC::ANDI_rec_1_EQ_BIT8 ||
12679 MI.getOpcode() == PPC::ANDI_rec_1_GT_BIT8) {
12680 unsigned Opcode = (
MI.getOpcode() == PPC::ANDI_rec_1_EQ_BIT8 ||
12681 MI.getOpcode() == PPC::ANDI_rec_1_GT_BIT8)
12684 bool IsEQ = (
MI.getOpcode() == PPC::ANDI_rec_1_EQ_BIT ||
12685 MI.getOpcode() == PPC::ANDI_rec_1_EQ_BIT8);
12688 Register Dest = RegInfo.createVirtualRegister(
12689 Opcode == PPC::ANDI_rec ? &PPC::GPRCRegClass : &PPC::G8RCRegClass);
12693 .
addReg(
MI.getOperand(1).getReg())
12696 MI.getOperand(0).getReg())
12698 }
else if (
MI.getOpcode() == PPC::TCHECK_RET) {
12701 Register CRReg = RegInfo.createVirtualRegister(&PPC::CRRCRegClass);
12704 MI.getOperand(0).getReg())
12706 }
else if (
MI.getOpcode() == PPC::TBEGIN_RET) {
12708 unsigned Imm =
MI.getOperand(1).getImm();
12711 MI.getOperand(0).getReg())
12713 }
else if (
MI.getOpcode() == PPC::SETRNDi) {
12729 unsigned Mode =
MI.getOperand(1).getImm();
12730 BuildMI(*BB,
MI, dl,
TII->get((Mode & 1) ? PPC::MTFSB1 : PPC::MTFSB0))
12733 BuildMI(*BB,
MI, dl,
TII->get((Mode & 2) ? PPC::MTFSB1 : PPC::MTFSB0))
12735 }
else if (
MI.getOpcode() == PPC::SETRND) {
12745 BuildMI(*BB,
MI, dl,
TII->get(TargetOpcode::COPY), DestReg)
12752 if (RC == &PPC::F8RCRegClass) {
12754 assert((RegInfo.getRegClass(DestReg) == &PPC::G8RCRegClass) &&
12755 "Unsupported RegClass.");
12761 assert((RegInfo.getRegClass(SrcReg) == &PPC::G8RCRegClass) &&
12762 (RegInfo.getRegClass(DestReg) == &PPC::F8RCRegClass) &&
12763 "Unsupported RegClass.");
12844 }
else if (
MI.getOpcode() == PPC::PROBED_ALLOCA_32 ||
12845 MI.getOpcode() == PPC::PROBED_ALLOCA_64) {
12851 MI.eraseFromParent();
12909unsigned PPCTargetLowering::combineRepeatedFPDivisors()
const {
12947 unsigned Bytes,
int Dist,
12961 if (FS !=
BFS || FS != (
int)Bytes)
return false;
12987 unsigned Bytes,
int Dist,
12990 EVT VT = LS->getMemoryVT();
12991 SDValue Loc = LS->getBasePtr();
12998 default:
return false;
12999 case Intrinsic::ppc_qpx_qvlfd:
13000 case Intrinsic::ppc_qpx_qvlfda:
13003 case Intrinsic::ppc_qpx_qvlfs:
13004 case Intrinsic::ppc_qpx_qvlfsa:
13007 case Intrinsic::ppc_qpx_qvlfcd:
13008 case Intrinsic::ppc_qpx_qvlfcda:
13011 case Intrinsic::ppc_qpx_qvlfcs:
13012 case Intrinsic::ppc_qpx_qvlfcsa:
13015 case Intrinsic::ppc_qpx_qvlfiwa:
13016 case Intrinsic::ppc_qpx_qvlfiwz:
13017 case Intrinsic::ppc_altivec_lvx:
13018 case Intrinsic::ppc_altivec_lvxl:
13019 case Intrinsic::ppc_vsx_lxvw4x:
13020 case Intrinsic::ppc_vsx_lxvw4x_be:
13023 case Intrinsic::ppc_vsx_lxvd2x:
13024 case Intrinsic::ppc_vsx_lxvd2x_be:
13027 case Intrinsic::ppc_altivec_lvebx:
13030 case Intrinsic::ppc_altivec_lvehx:
13033 case Intrinsic::ppc_altivec_lvewx:
13044 default:
return false;
13045 case Intrinsic::ppc_qpx_qvstfd:
13046 case Intrinsic::ppc_qpx_qvstfda:
13049 case Intrinsic::ppc_qpx_qvstfs:
13050 case Intrinsic::ppc_qpx_qvstfsa:
13053 case Intrinsic::ppc_qpx_qvstfcd:
13054 case Intrinsic::ppc_qpx_qvstfcda:
13057 case Intrinsic::ppc_qpx_qvstfcs:
13058 case Intrinsic::ppc_qpx_qvstfcsa:
13061 case Intrinsic::ppc_qpx_qvstfiw:
13062 case Intrinsic::ppc_qpx_qvstfiwa:
13063 case Intrinsic::ppc_altivec_stvx:
13064 case Intrinsic::ppc_altivec_stvxl:
13065 case Intrinsic::ppc_vsx_stxvw4x:
13068 case Intrinsic::ppc_vsx_stxvd2x:
13071 case Intrinsic::ppc_vsx_stxvw4x_be:
13074 case Intrinsic::ppc_vsx_stxvd2x_be:
13077 case Intrinsic::ppc_altivec_stvebx:
13080 case Intrinsic::ppc_altivec_stvehx:
13083 case Intrinsic::ppc_altivec_stvewx:
13100 SDValue Chain = LD->getChain();
13101 EVT VT = LD->getMemoryVT();
13110 while (!Queue.empty()) {
13119 if (!Visited.count(
ChainLD->getChain().getNode()))
13120 Queue.push_back(
ChainLD->getChain().getNode());
13123 if (!Visited.count(O.getNode()))
13124 Queue.push_back(O.getNode());
13139 Queue.push_back(*
I);
13141 while (!Queue.empty()) {
13143 if (!Visited.insert(
LoadRoot).second)
13151 UE =
LoadRoot->use_end(); UI != UE; ++UI)
13155 Queue.push_back(*UI);
13199 DAGCombinerInfo &
DCI)
const {
13207 if (!
DCI.isAfterLegalizeDAG())
13213 UE =
N->
use_end(); UI != UE; ++UI) {
13219 auto OpSize =
N->getOperand(0).getValueSizeInBits();
13241 DAGCombinerInfo &
DCI)
const {
13259 if (
N->getOperand(0).getValueType() !=
MVT::i32 &&
13260 N->getOperand(0).getValueType() !=
MVT::i64)
13270 unsigned OpBits =
N->getOperand(0).getValueSizeInBits();
13281 return (
N->getOpcode() ==
ISD::SETCC ? ConvertSETCCToSubtract(
N,
DCI)
13302 if (
N->getOperand(0).getOpcode() !=
ISD::AND &&
13303 N->getOperand(0).getOpcode() !=
ISD::OR &&
13304 N->getOperand(0).getOpcode() !=
ISD::XOR &&
13314 N->getOperand(1).getOpcode() !=
ISD::AND &&
13315 N->getOperand(1).getOpcode() !=
ISD::OR &&
13316 N->getOperand(1).getOpcode() !=
ISD::XOR &&
13329 for (
unsigned i = 0;
i < 2; ++
i) {
13333 N->getOperand(
i).getOperand(0).getValueType() ==
MVT::i1) ||
13335 Inputs.push_back(
N->getOperand(
i));
13337 BinOps.push_back(
N->getOperand(
i));
13345 while (!
BinOps.empty()) {
13349 if (!Visited.insert(BinOp.
getNode()).second)
13388 for (
unsigned i = 0,
ie = Inputs.size();
i !=
ie; ++
i) {
13393 UE = Inputs[
i].getNode()->use_end();
13417 UE =
PromOps[
i].getNode()->use_end();
13440 for (
unsigned i = 0,
ie = Inputs.size();
i !=
ie; ++
i) {
13482 switch (
PromOp.getOpcode()) {
13483 default:
C = 0;
break;
13501 PromOp.getNode()->op_end());
13504 for (
unsigned i = 0;
i < 2; ++
i)
13514 return N->getOperand(0);
13522 DAGCombinerInfo &
DCI)
const {
13548 if (
N->getOperand(0).getOpcode() !=
ISD::AND &&
13549 N->getOperand(0).getOpcode() !=
ISD::OR &&
13550 N->getOperand(0).getOpcode() !=
ISD::XOR &&
13561 while (!
BinOps.empty()) {
13565 if (!Visited.insert(BinOp.
getNode()).second)
13601 for (
unsigned i = 0,
ie = Inputs.size();
i !=
ie; ++
i) {
13606 UE = Inputs[
i].getNode()->use_end();
13631 UE =
PromOps[
i].getNode()->use_end();
13654 unsigned PromBits =
N->getOperand(0).getValueSizeInBits();
13659 for (
unsigned i = 0,
ie = Inputs.size();
i !=
ie; ++
i) {
13664 Inputs[
i].getOperand(0).getValueSizeInBits();
13682 for (
unsigned i = 0,
ie = Inputs.size();
i !=
ie; ++
i) {
13716 switch (
PromOp.getOpcode()) {
13717 default:
C = 0;
break;
13723 PromOp.getOperand(
C).getValueType() !=
N->getValueType(0)) ||
13725 PromOp.getOperand(
C+1).getValueType() !=
N->getValueType(0))) {
13739 PromOp.getOperand(0).getValueType() !=
N->getValueType(0)) ||
13741 PromOp.getOperand(1).getValueType() !=
N->getValueType(0))) {
13748 PromOp.getNode()->op_end());
13751 for (
unsigned i = 0;
i < 2; ++
i) {
13783 return N->getOperand(0);
13791 dl,
N->getValueType(0)));
13794 "Invalid extension type");
13805 DAGCombinerInfo &
DCI)
const {
13807 "Should be called with a SETCC node");
13825 EVT VT =
N->getValueType(0);
13832 return DAGCombineTruncBoolExt(
N,
DCI);
13851combineElementTruncationToVectorTruncation(
SDNode *
N,
13852 DAGCombinerInfo &
DCI)
const {
13854 "Should be called with a BUILD_VECTOR node");
13861 "The input operand must be an fp-to-int conversion.");
13870 bool IsSplat =
true;
13876 for (
int i = 0, e =
N->getNumOperands();
i <
e; ++
i) {
13900 for (
int i = 0, e =
N->getNumOperands();
i <
e; ++
i) {
13911 Ops.push_back(Trunc);
13939 "Should be called with a BUILD_VECTOR node");
13944 if (!
N->getValueType(0).getVectorElementType().isByteSized())
13949 unsigned ElemSize =
N->getValueType(0).getScalarType().getStoreSize();
13960 N->getNumOperands() == 1)
13963 for (
int i = 1, e =
N->getNumOperands();
i < e; ++
i) {
13993 "The loads cannot be both consecutive and reverse consecutive.");
13999 N->getOperand(
N->getNumOperands()-1);
14004 assert(
LD1 &&
"Input needs to be a LoadSDNode.");
14005 return DAG.
getLoad(
N->getValueType(0), dl,
LD1->getChain(),
14006 LD1->getBasePtr(),
LD1->getPointerInfo(),
14007 LD1->getAlignment());
14010 assert(LDL &&
"Input needs to be a LoadSDNode.");
14012 LDL->getBasePtr(), LDL->getPointerInfo(),
14013 LDL->getAlignment());
14015 for (
int i =
N->getNumOperands() - 1;
i >= 0;
i--)
14019 DAG.
getUNDEF(
N->getValueType(0)), Ops);
14032 unsigned NumElems = Input.getValueType().getVectorNumElements();
14038 for (
unsigned i = 0;
i <
N->getNumOperands();
i++) {
14049 DAG.
getUNDEF(Input.getValueType()), ShuffleMask);
14051 EVT VT =
N->getValueType(0);
14055 Input.getValueType().getVectorElementType(),
14085 uint64_t
Elems = 0;
14098 SDValue Extract = Op.getOperand(0);
14108 Index =
ExtOp->getZExtValue();
14109 if (Input && Input != Extract.
getOperand(0))
14124 for (
unsigned i = 0;
i <
N->getNumOperands();
i++) {
14133 int InputSize = Input.getValueType().getScalarSizeInBits();
14134 int OutputSize =
N->getValueType(0).getScalarSizeInBits();
14161 DAGCombinerInfo &
DCI)
const {
14163 "Should be called with a BUILD_VECTOR node");
14168 if (!Subtarget.
hasVSX())
14209 if (
FirstInput.getOpcode() !=
N->getOperand(1).getOpcode())
14223 Ext1.getOperand(0) !=
Ext2.getOperand(0))
14244 DAGCombinerInfo &
DCI)
const {
14247 "Need an int -> FP conversion node here");
14260 if (
Op.getOperand(0).getValueType().getSimpleVT() <=
MVT(
MVT::i1) ||
14261 Op.getOperand(0).getValueType().getSimpleVT() >
MVT(
MVT::i64))
14297 if (
Op.getOperand(0).getValueType() ==
MVT::i32)
14301 "UINT_TO_FP is supported only with FPCVT");
14319 SDValue Src =
Op.getOperand(0).getOperand(0);
14338 DCI.AddToWorklist(
FP.getNode());
14357 switch (
N->getOpcode()) {
14362 Chain = LD->getChain();
14363 Base = LD->getBasePtr();
14364 MMO = LD->getMemOperand();
14374 Chain =
Intrin->getChain();
14377 Base =
Intrin->getOperand(2);
14378 MMO =
Intrin->getMemOperand();
14383 MVT VecTy =
N->getValueType(0).getSimpleVT();
14397 DCI.AddToWorklist(Load.getNode());
14398 Chain = Load.getValue(1);
14406 DCI.AddToWorklist(
N.getNode());
14426 switch (
N->getOpcode()) {
14431 Chain = ST->getChain();
14432 Base = ST->getBasePtr();
14433 MMO = ST->getMemOperand();
14444 Chain =
Intrin->getChain();
14446 Base =
Intrin->getOperand(3);
14447 MMO =
Intrin->getMemOperand();
14477 DCI.AddToWorklist(Store.getNode());
14483 DAGCombinerInfo &
DCI)
const {
14487 unsigned Opcode =
N->getOperand(1).getOpcode();
14490 &&
"Not a FP_TO_INT Instruction!");
14493 EVT Op1VT =
N->getOperand(1).getValueType();
14497 if (
ResVT.getScalarSizeInBits() < 32)
14510 if (
ResVT.getScalarSizeInBits() == 32) {
14518 PPCISD::FP_TO_UINT_IN_VSR;
14525 unsigned ByteSize =
Op1VT.getScalarSizeInBits() / 8;
14543 for (
int i = 1, e = Mask.size();
i < e;
i++) {
14559 for (
int i = 0, e = Op.getNumOperands();
i < e;
i++) {
14560 FirstOp = Op.getOperand(
i);
14566 for (
int i = 1, e = Op.getNumOperands();
i < e;
i++)
14567 if (Op.getOperand(
i) != FirstOp && !Op.getOperand(
i).isUndef())
14577 Op = Op.getOperand(0);
14586 for (
int i = 0, e =
ShuffV.size();
i < e;
i++) {
14603 "Expecting a SCALAR_TO_VECTOR here");
14662 :
SToVRHS.getValueType().getVectorNumElements();
14726 for (
int i = 1, e =
Mask.size();
i <
e;
i += 2)
14731 for (
int i = 0, e =
Mask.size();
i <
e;
i += 2)
14745 DAGCombinerInfo &
DCI)
const {
14747 "Not a reverse memop pattern!");
14752 auto I =
Mask.rbegin();
14753 auto E =
Mask.rend();
14755 for (;
I !=
E; ++
I) {
14764 EVT VT =
SVN->getValueType(0);
14802 switch (
N->getOpcode()) {
14805 return combineADD(
N,
DCI);
14807 return combineSHL(
N,
DCI);
14809 return combineSRA(
N,
DCI);
14811 return combineSRL(
N,
DCI);
14813 return combineMUL(
N,
DCI);
14816 return combineFMALike(
N,
DCI);
14819 return N->getOperand(0);
14823 return N->getOperand(0);
14827 if (
C->isNullValue() ||
14828 C->isAllOnesValue())
14829 return N->getOperand(0);
14835 return DAGCombineExtBoolTrunc(
N,
DCI);
14837 return combineTRUNCATE(
N,
DCI);
14843 return DAGCombineTruncBoolExt(
N,
DCI);
14846 return combineFPToIntToFP(
N,
DCI);
14855 EVT Op1VT =
N->getOperand(1).getValueType();
14856 unsigned Opcode =
N->getOperand(1).getOpcode();
14873 N->getOperand(1).getNode()->hasOneUse() &&
14880 if (
mVT.isExtended() ||
mVT.getSizeInBits() < 16)
14891 int Shift =
Op1VT.getSizeInBits() -
mVT.getSizeInBits();
14910 if (Subtarget.
isPPC64() && !
DCI.isBeforeLegalize() &&
14915 MemVT.getSizeInBits());
14929 if (
Op1VT.isSimple()) {
14940 EVT VT = LD->getValueType(0);
14975 if (!LD->hasNUsesOfValue(2, 0))
14978 auto UI = LD->use_begin();
14979 while (UI.getUse().getResNo() != 0) ++UI;
14981 while (UI.getUse().getResNo() != 0) ++UI;
14982 SDNode *RightShift = *UI;
14990 if (RightShift->getOpcode() !=
ISD::SRL ||
14992 RightShift->getConstantOperandVal(1) != 32 ||
14993 !RightShift->hasOneUse())
15006 Bitcast->getValueType(0) !=
MVT::f32)
15018 SDValue BasePtr = LD->getBasePtr();
15019 if (LD->isIndexed()) {
15021 "Non-pre-inc AM on PPC?");
15030 LD->getPointerInfo(), LD->getAlignment(),
15031 MMOFlags, LD->getAAInfo());
15037 LD->getPointerInfo().getWithOffset(4),
15038 MinAlign(LD->getAlignment(), 4), MMOFlags, LD->getAAInfo());
15040 if (LD->isIndexed()) {
15062 if (LD->isUnindexed() && VT.
isVector() &&
15072 SDValue Chain = LD->getChain();
15073 SDValue Ptr = LD->getBasePtr();
15103 Intr = isLittleEndian ? Intrinsic::ppc_altivec_lvsr :
15104 Intrinsic::ppc_altivec_lvsl;
15105 IntrLD = Intrinsic::ppc_altivec_lvx;
15106 IntrPerm = Intrinsic::ppc_altivec_vperm;
15112 Intrinsic::ppc_qpx_qvlpcls;
15114 Intrinsic::ppc_qpx_qvlfs;
15115 IntrPerm = Intrinsic::ppc_qpx_qvfperm;
15131 -(
long)
MemVT.getStoreSize()+1,
15132 2*
MemVT.getStoreSize()-1);
15166 1, 2*
MemVT.getStoreSize()-1);
15182 if (isLittleEndian)
15208 : Intrinsic::ppc_altivec_lvsl);
15209 if ((IID ==
Intr ||
15210 IID == Intrinsic::ppc_qpx_qvlpcld ||
15211 IID == Intrinsic::ppc_qpx_qvlpcls) &&
15212 N->getOperand(1)->getOpcode() ==
ISD::ADD) {
15215 int Bits = IID == Intrinsic::ppc_qpx_qvlpcld ?
15220 .zext(Add.getScalarValueSizeInBits()))) {
15221 SDNode *BasePtr = Add->getOperand(0).getNode();
15223 UE = BasePtr->use_end();
15237 SDNode *BasePtr = Add->getOperand(0).getNode();
15239 UE = BasePtr->use_end(); UI != UE; ++UI) {
15240 if (UI->getOpcode() ==
ISD::ADD &&
15244 (1ULL << Bits) == 0) {
15261 (IID == Intrinsic::ppc_altivec_vmaxsw ||
15262 IID == Intrinsic::ppc_altivec_vmaxsh ||
15263 IID == Intrinsic::ppc_altivec_vmaxsb)) {
15269 V1.getSimpleValueType() == V2.getSimpleValueType()) {
15273 V1.getOperand(1) == V2) {
15279 V2.getOperand(1) ==
V1) {
15284 V1.getOperand(0) == V2.getOperand(1) &&
15285 V1.getOperand(1) == V2.getOperand(0)) {
15300 case Intrinsic::ppc_vsx_lxvw4x:
15301 case Intrinsic::ppc_vsx_lxvd2x:
15313 case Intrinsic::ppc_vsx_stxvw4x:
15314 case Intrinsic::ppc_vsx_stxvd2x:
15322 N->getOperand(0).hasOneUse() &&
15338 Ops, LD->getMemoryVT(), LD->getMemOperand());
15362 if (!
N->getOperand(0).hasOneUse() &&
15363 !
N->getOperand(1).hasOneUse() &&
15364 !
N->getOperand(2).hasOneUse()) {
15373 UI->getOperand(1) ==
N->getOperand(1) &&
15374 UI->getOperand(2) ==
N->getOperand(2) &&
15375 UI->getOperand(0) ==
N->getOperand(0)) {
15413 Intrinsic::loop_decrement) {
15419 "Counter decrement has more than one use");
15439 Intrinsic::loop_decrement &&
15446 Intrinsic::loop_decrement &&
15449 "Counter decrement comparison is not EQ or NE");
15459 "Counter decrement has more than one use");
15462 N->getOperand(0),
N->getOperand(4));
15471 assert(
isDot &&
"Can't compare against a vector result!");
15476 if (Val != 0 && Val != 1) {
15478 return N->getOperand(0);
15481 N->getOperand(0),
N->getOperand(4));
15521 return DAGCombineBuildVector(
N,
DCI);
15523 return combineABS(
N,
DCI);
15525 return combineVSelect(
N,
DCI);
15536 EVT VT =
N->getValueType(0);
15540 !(Divisor.
isPowerOf2() || (-Divisor).isPowerOf2()))
15546 bool IsNegPow2 = (-Divisor).isPowerOf2();
15551 Created.push_back(Op.getNode());
15555 Created.push_back(Op.getNode());
15569 unsigned Depth)
const {
15571 switch (Op.getOpcode()) {
15576 Known.
Zero = 0xFFFF0000;
15582 case Intrinsic::ppc_altivec_vcmpbfp_p:
15583 case Intrinsic::ppc_altivec_vcmpeqfp_p:
15584 case Intrinsic::ppc_altivec_vcmpequb_p:
15585 case Intrinsic::ppc_altivec_vcmpequh_p:
15586 case Intrinsic::ppc_altivec_vcmpequw_p:
15587 case Intrinsic::ppc_altivec_vcmpequd_p:
15588 case Intrinsic::ppc_altivec_vcmpgefp_p:
15589 case Intrinsic::ppc_altivec_vcmpgtfp_p:
15590 case Intrinsic::ppc_altivec_vcmpgtsb_p:
15591 case Intrinsic::ppc_altivec_vcmpgtsh_p:
15592 case Intrinsic::ppc_altivec_vcmpgtsw_p:
15593 case Intrinsic::ppc_altivec_vcmpgtsd_p:
15594 case Intrinsic::ppc_altivec_vcmpgtub_p:
15595 case Intrinsic::ppc_altivec_vcmpgtuh_p:
15596 case Intrinsic::ppc_altivec_vcmpgtuw_p:
15597 case Intrinsic::ppc_altivec_vcmpgtud_p:
15637 for (
auto J = (*I)->begin(),
JE = (*I)->end(); J !=
JE; ++J) {
15657 if (Constraint.
size() == 1) {
15658 switch (Constraint[0]) {
15676 }
else if (Constraint ==
"wc") {
15678 }
else if (Constraint ==
"wa" || Constraint ==
"wd" ||
15679 Constraint ==
"wf" || Constraint ==
"ws" ||
15680 Constraint ==
"wi" || Constraint ==
"ww") {
15693 Value *CallOperandVal =
info.CallOperandVal;
15696 if (!CallOperandVal)
15745std::pair<unsigned, const TargetRegisterClass *>
15749 if (Constraint.
size() == 1) {
15751 switch (Constraint[0]) {
15754 return std::make_pair(0U, &PPC::G8RC_NOX0RegClass);
15755 return std::make_pair(0U, &PPC::GPRC_NOR0RegClass);
15758 return std::make_pair(0U, &PPC::G8RCRegClass);
15759 return std::make_pair(0U, &PPC::GPRCRegClass);
15765 if (Subtarget.
hasSPE()) {
15767 return std::make_pair(0U, &PPC::GPRCRegClass);
15769 return std::make_pair(0U, &PPC::SPERCRegClass);
15772 return std::make_pair(0U, &PPC::F4RCRegClass);
15774 return std::make_pair(0U, &PPC::F8RCRegClass);
15776 return std::make_pair(0U, &PPC::QFRCRegClass);
15778 return std::make_pair(0U, &PPC::QSRCRegClass);
15783 return std::make_pair(0U, &PPC::QFRCRegClass);
15785 return std::make_pair(0U, &PPC::QSRCRegClass);
15787 return std::make_pair(0U, &PPC::VRRCRegClass);
15790 return std::make_pair(0U, &PPC::CRRCRegClass);
15792 }
else if (Constraint ==
"wc" && Subtarget.
useCRBits()) {
15794 return std::make_pair(0U, &PPC::CRBITRCRegClass);
15795 }
else if ((Constraint ==
"wa" || Constraint ==
"wd" ||
15796 Constraint ==
"wf" || Constraint ==
"wi") &&
15798 return std::make_pair(0U, &PPC::VSRCRegClass);
15799 }
else if ((Constraint ==
"ws" || Constraint ==
"ww") && Subtarget.
hasVSX()) {
15801 return std::make_pair(0U, &PPC::VSSRCRegClass);
15803 return std::make_pair(0U, &PPC::VSFRCRegClass);
15809 if (Constraint.
size() > 3 && Constraint[1] ==
'v' && Constraint[2] ==
's') {
15812 "Attempted to access a vsr out of range");
15814 return std::make_pair(PPC::VSL0 +
VSNum, &PPC::VSRCRegClass);
15815 return std::make_pair(PPC::V0 +
VSNum - 32, &PPC::VSRCRegClass);
15817 std::pair<unsigned, const TargetRegisterClass *> R =
15827 PPC::GPRCRegClass.contains(R.first))
15828 return std::make_pair(
TRI->getMatchingSuperReg(R.first,
15829 PPC::sub_32, &PPC::G8RCRegClass),
15830 &PPC::G8RCRegClass);
15833 if (!R.second &&
StringRef(
"{cc}").equals_lower(Constraint)) {
15834 R.first = PPC::CR0;
15835 R.second = &PPC::CRRCRegClass;
15844 std::string &Constraint,
15845 std::vector<SDValue>&Ops,
15850 if (Constraint.length() > 1)
return;
15852 char Letter = Constraint[0];
15866 int64_t
Value =
CST->getSExtValue();
15908 if (Result.getNode()) {
15909 Ops.push_back(Result);
15923 if (Ty->isVectorTy() && AM.
BaseOffs != 0)
15935 switch (AM.
Scale) {
15972 bool isPPC64 = Subtarget.
isPPC64();
16007 FrameReg = isPPC64 ? PPC::X1 : PPC::R1;
16009 FrameReg = isPPC64 ? PPC::FP8 : PPC::FP;
16023 bool isPPC64 = Subtarget.
isPPC64();
16030 .Case(
"r1",
is64Bit ? PPC::X1 : PPC::R1)
16031 .Case(
"r2", isPPC64 ?
Register() : PPC::R2)
16032 .Case(
"r13", (
is64Bit ? PPC::X13 : PPC::R13))
16075 unsigned Intrinsic)
const {
16076 switch (Intrinsic) {
16077 case Intrinsic::ppc_qpx_qvlfd:
16078 case Intrinsic::ppc_qpx_qvlfs:
16079 case Intrinsic::ppc_qpx_qvlfcd:
16080 case Intrinsic::ppc_qpx_qvlfcs:
16081 case Intrinsic::ppc_qpx_qvlfiwa:
16082 case Intrinsic::ppc_qpx_qvlfiwz:
16083 case Intrinsic::ppc_altivec_lvx:
16084 case Intrinsic::ppc_altivec_lvxl:
16085 case Intrinsic::ppc_altivec_lvebx:
16086 case Intrinsic::ppc_altivec_lvehx:
16087 case Intrinsic::ppc_altivec_lvewx:
16088 case Intrinsic::ppc_vsx_lxvd2x:
16089 case Intrinsic::ppc_vsx_lxvw4x: {
16091 switch (Intrinsic) {
16092 case Intrinsic::ppc_altivec_lvebx:
16095 case Intrinsic::ppc_altivec_lvehx:
16098 case Intrinsic::ppc_altivec_lvewx:
16101 case Intrinsic::ppc_vsx_lxvd2x:
16104 case Intrinsic::ppc_qpx_qvlfd:
16107 case Intrinsic::ppc_qpx_qvlfs:
16110 case Intrinsic::ppc_qpx_qvlfcd:
16113 case Intrinsic::ppc_qpx_qvlfcs:
16123 Info.ptrVal =
I.getArgOperand(0);
16126 Info.align =
Align(1);
16130 case Intrinsic::ppc_qpx_qvlfda:
16131 case Intrinsic::ppc_qpx_qvlfsa:
16132 case Intrinsic::ppc_qpx_qvlfcda:
16133 case Intrinsic::ppc_qpx_qvlfcsa:
16134 case Intrinsic::ppc_qpx_qvlfiwaa:
16135 case Intrinsic::ppc_qpx_qvlfiwza: {
16137 switch (Intrinsic) {
16138 case Intrinsic::ppc_qpx_qvlfda:
16141 case Intrinsic::ppc_qpx_qvlfsa:
16144 case Intrinsic::ppc_qpx_qvlfcda:
16147 case Intrinsic::ppc_qpx_qvlfcsa:
16157 Info.ptrVal =
I.getArgOperand(0);
16160 Info.align =
Align(1);
16164 case Intrinsic::ppc_qpx_qvstfd:
16165 case Intrinsic::ppc_qpx_qvstfs:
16166 case Intrinsic::ppc_qpx_qvstfcd:
16167 case Intrinsic::ppc_qpx_qvstfcs:
16168 case Intrinsic::ppc_qpx_qvstfiw:
16169 case Intrinsic::ppc_altivec_stvx:
16170 case Intrinsic::ppc_altivec_stvxl:
16171 case Intrinsic::ppc_altivec_stvebx:
16172 case Intrinsic::ppc_altivec_stvehx:
16173 case Intrinsic::ppc_altivec_stvewx:
16174 case Intrinsic::ppc_vsx_stxvd2x:
16175 case Intrinsic::ppc_vsx_stxvw4x: {
16177 switch (Intrinsic) {
16178 case Intrinsic::ppc_altivec_stvebx:
16181 case Intrinsic::ppc_altivec_stvehx:
16184 case Intrinsic::ppc_altivec_stvewx:
16187 case Intrinsic::ppc_vsx_stxvd2x:
16190 case Intrinsic::ppc_qpx_qvstfd:
16193 case Intrinsic::ppc_qpx_qvstfs:
16196 case Intrinsic::ppc_qpx_qvstfcd:
16199 case Intrinsic::ppc_qpx_qvstfcs:
16209 Info.ptrVal =
I.getArgOperand(1);
16212 Info.align =
Align(1);
16216 case Intrinsic::ppc_qpx_qvstfda:
16217 case Intrinsic::ppc_qpx_qvstfsa:
16218 case Intrinsic::ppc_qpx_qvstfcda:
16219 case Intrinsic::ppc_qpx_qvstfcsa:
16220 case Intrinsic::ppc_qpx_qvstfiwa: {
16222 switch (Intrinsic) {
16223 case Intrinsic::ppc_qpx_qvstfda:
16226 case Intrinsic::ppc_qpx_qvstfsa:
16229 case Intrinsic::ppc_qpx_qvstfcda:
16232 case Intrinsic::ppc_qpx_qvstfcsa:
16242 Info.ptrVal =
I.getArgOperand(1);
16245 Info.align =
Align(1);
16263 if (Subtarget.
hasQPX() && Op.size() >= 32 &&
16264 (Op.isMemcpy() || Op.size() >= 64) && Op.isAligned(
Align(32)) &&
16271 if (Subtarget.
hasAltivec() && Op.size() >= 16 &&
16272 (Op.isAligned(
Align(16)) ||
16288 assert(Ty->isIntegerTy());
16290 unsigned BitSize = Ty->getPrimitiveSizeInBits();
16291 return !(BitSize == 0 || BitSize > 64);
16295 if (!
Ty1->isIntegerTy() || !
Ty2->isIntegerTy())
16297 unsigned NumBits1 =
Ty1->getPrimitiveSizeInBits();
16298 unsigned NumBits2 =
Ty2->getPrimitiveSizeInBits();
16303 if (!
VT1.isInteger() || !
VT2.isInteger())
16332 "invalid fpext types");
16351 bool *Fast)
const {
16369 if (Subtarget.
hasVSX()) {
16395 switch (Ty->getScalarType()->getTypeID()) {
16412 if (!
I->hasOneUse())
16416 assert(
User &&
"A single use instruction with no uses.");
16418 if (
User->getOpcode() != Instruction::FSub &&
16419 User->getOpcode() != Instruction::FAdd)
16440 PPC::X12, PPC::LR8, PPC::CTR8, 0
16447 const Constant *PersonalityFn)
const {
16448 return Subtarget.
isPPC64() ? PPC::X3 : PPC::R3;
16452 const Constant *PersonalityFn)
const {
16453 return Subtarget.
isPPC64() ? PPC::X4 : PPC::R4;
16496 bool LegalOps,
bool OptForSize,
16498 unsigned Depth)
const {
16502 unsigned Opc = Op.getOpcode();
16503 EVT VT = Op.getValueType();
16513 SDValue N0 = Op.getOperand(0);
16515 SDValue N2 = Op.getOperand(2);
16542 }
else if (
NegN1) {
16575 bool ForCodeSize)
const {
16606 unsigned Opcode =
N->getOpcode();
16607 unsigned TargetOpcode;
16627 return DAG.
getNode(TargetOpcode,
SDLoc(
N), VT, N0,
N1->getOperand(0));
16693 SDValue Cmp = Op.getOperand(0);
16694 if (Cmp.getOpcode() !=
ISD::SETCC || !Cmp.hasOneUse() ||
16695 Cmp.getOperand(0).getValueType() !=
MVT::i64)
16829 DAGCombinerInfo &
DCI)
const {
16842 EVT VT =
N->getValueType(0);
16882 return DCI.DAG.getNode(
16928 EVT VT =
N->getValueType(0);
16952 }
else if ((
MulAmtAbs + 1).isPowerOf2()) {
16977 DAGCombinerInfo &
DCI)
const {
16982 EVT VT =
N->getValueType(0);
16985 unsigned Opc =
N->getOpcode();
16987 bool LegalOps = !
DCI.isBeforeLegalizeOps();
17012bool PPCTargetLowering::mayBeEmittedAsTailCall(
const CallInst *CI)
const {
17042bool PPCTargetLowering::hasBitPreservingFPLogic(
EVT VT)
const {
17043 if (!Subtarget.
hasVSX())
17051bool PPCTargetLowering::
17057 if (CI->getBitWidth() > 64)
17059 int64_t ConstVal = CI->getZExtValue();
17061 (
isUInt<16>(ConstVal >> 16) && !(ConstVal & 0xFFFF));
17076 "Only combine this when P9 altivec supported!");
17077 EVT VT =
N->getValueType(0);
17083 if (
N->getOperand(0).getOpcode() ==
ISD::SUB) {
17086 unsigned SubOpcd0 =
N->getOperand(0)->getOperand(0).getOpcode();
17087 unsigned SubOpcd1 =
N->getOperand(0)->getOperand(1).getOpcode();
17093 N->getOperand(0)->getOperand(0),
17094 N->getOperand(0)->getOperand(1),
17099 if (
N->getOperand(0).getValueType() ==
MVT::v4i32 &&
17100 N->getOperand(0).hasOneUse()) {
17102 N->getOperand(0)->getOperand(0),
17103 N->getOperand(0)->getOperand(1),
17117 DAGCombinerInfo &
DCI)
const {
17120 "Only combine this when P9 altivec supported!");
17127 EVT VT =
N->getOperand(1).getValueType();
unsigned const MachineRegisterInfo * MRI
static unsigned getCallOpcode(const MachineFunction &CallerF, bool IsIndirect, bool IsTailCall)
static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS, SDValue RHS, SelectionDAG &DAG, const SDLoc &dl)
GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit the specified operations t...
static const unsigned PerfectShuffleTable[6561+1]
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
amdgpu Simplify well known AMD library false FunctionCallee Callee
amdgpu Simplify well known AMD library false FunctionCallee Value * Arg
static std::pair< Register, unsigned > getBaseWithConstantOffset(MachineRegisterInfo &MRI, Register Reg)
This file declares a class to represent arbitrary precision floating point values and provide a varie...
This file implements a class to represent arbitrary precision integral constant values and operations...
static bool isLoad(int Opcode)
static bool isFloatingPointZero(SDValue Op)
isFloatingPointZero - Return true if this is +0.0.
Function Alias Analysis Results
Atomic ordering constants.
SmallVector< MachineOperand, 4 > Cond
static GCRegistry::Add< ShadowStackGC > C("shadow-stack", "Very portable GC for uncooperative code generators")
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Analysis containing CSE Info
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
This file contains the declarations for the subclasses of Constant, which represent the different fla...
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
static RegisterPass< DebugifyModulePass > DM("debugify", "Attach debug info to everything")
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
const HexagonInstrInfo * TII
static SDValue CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, ISD::ArgFlagsTy Flags, SelectionDAG &DAG, const SDLoc &dl)
CreateCopyOfByValArgument - Make a copy of an aggregate at address specified by "Src" to address "Dst...
unsigned const TargetRegisterInfo * TRI
Promote Memory to Register
static bool isConstantOrUndef(const SDValue Op)
Module.h This file contains the declarations for the Module class.
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
cl::opt< bool > ANDIGlueBug("expose-ppc-andi-glue-bug", cl::desc("expose the ANDI glue bug on PPC"), cl::Hidden)
static SDValue getCanonicalConstSplat(uint64_t Val, unsigned SplatSize, EVT VT, SelectionDAG &DAG, const SDLoc &dl)
getCanonicalConstSplat - Build a canonical splat immediate of Val with an element size of SplatSize.
static const MCPhysReg QFPR[]
QFPR - The set of QPX registers that should be allocated for arguments.
static bool needStackSlotPassParameters(const PPCSubtarget &Subtarget, const SmallVectorImpl< ISD::OutputArg > &Outs)
static void fixupShuffleMaskForPermutedSToV(SmallVectorImpl< int > &ShuffV, int LHSMaxIdx, int RHSMinIdx, int RHSMaxIdx, int HalfVec)
static bool isAlternatingShuffMask(const ArrayRef< int > &Mask, int NumElts)
static SDValue addShuffleForVecExtend(SDNode *N, SelectionDAG &DAG, SDValue Input, uint64_t Elems, uint64_t CorrectElems)
static cl::opt< bool > DisablePPCUnaligned("disable-ppc-unaligned", cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden)
static SDValue combineADDToADDZE(SDNode *N, SelectionDAG &DAG, const PPCSubtarget &Subtarget)
static bool findConsecutiveLoad(LoadSDNode *LD, SelectionDAG &DAG)
static SDValue generateEquivalentSub(SDNode *N, int Size, bool Complement, bool Swap, SDLoc &DL, SelectionDAG &DAG)
This function is called when we have proved that a SETCC node can be replaced by subtraction (and oth...
static unsigned mapArgRegToOffsetAIX(unsigned Reg, const PPCFrameLowering *FL)
static bool callsShareTOCBase(const Function *Caller, SDValue Callee, const TargetMachine &TM)
static SDValue combineADDToMAT_PCREL_ADDR(SDNode *N, SelectionDAG &DAG, const PPCSubtarget &Subtarget)
static bool isTOCSaveRestoreRequired(const PPCSubtarget &Subtarget)
static bool isFunctionGlobalAddress(SDValue Callee)
static void CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64, SDValue Arg, int SPDiff, unsigned ArgOffset, SmallVectorImpl< TailCallArgumentInfo > &TailCallArguments)
CalculateTailCallArgDest - Remember Argument for later processing.
static void LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain, SDValue Arg, SDValue PtrOff, int SPDiff, unsigned ArgOffset, bool isPPC64, bool isTailCall, bool isVector, SmallVectorImpl< SDValue > &MemOpChains, SmallVectorImpl< TailCallArgumentInfo > &TailCallArguments, const SDLoc &dl)
LowerMemOpCallTo - Store the argument to the stack or remember it in case of tail calls.
static bool CalculateStackSlotUsed(EVT ArgVT, EVT OrigVT, ISD::ArgFlagsTy Flags, unsigned PtrByteSize, unsigned LinkageSize, unsigned ParamAreaSize, unsigned &ArgOffset, unsigned &AvailableFPRs, unsigned &AvailableVRs, bool HasQPX)
CalculateStackSlotUsed - Return whether this argument will use its stack slot (instead of being passe...
static bool areCallingConvEligibleForTCO_64SVR4(CallingConv::ID CallerCC, CallingConv::ID CalleeCC)
static const MCPhysReg FPR[]
FPR - The set of FP registers that should be allocated for arguments on Darwin and AIX.
static SDNode * isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG)
isCallCompatibleAddress - Return the immediate to use if the specified 32-bit value is representable ...
static Align CalculateStackSlotAlignment(EVT ArgVT, EVT OrigVT, ISD::ArgFlagsTy Flags, unsigned PtrByteSize)
CalculateStackSlotAlignment - Calculates the alignment of this argument on the stack.
static bool haveEfficientBuildVectorPattern(BuildVectorSDNode *V, bool HasDirectMove, bool HasP8Vector)
Do we have an efficient pattern in a .td file for this node?
static void setUsesTOCBasePtr(MachineFunction &MF)
static SDValue transformCallee(const SDValue &Callee, SelectionDAG &DAG, const SDLoc &dl, const PPCSubtarget &Subtarget)
static bool CC_AIX(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
static unsigned EnsureStackAlignment(const PPCFrameLowering *Lowering, unsigned NumBytes)
EnsureStackAlignment - Round stack frame size up from NumBytes to ensure minimum alignment required f...
static SDValue stripModuloOnShift(const TargetLowering &TLI, SDNode *N, SelectionDAG &DAG)
static bool hasSameArgumentList(const Function *CallerFn, const CallBase &CB)
static bool isFPExtLoad(SDValue Op)
static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op, SelectionDAG &DAG, const SDLoc &dl, EVT DestVT=MVT::Other)
BuildIntrinsicOp - Return a unary operator intrinsic node with the specified intrinsic ID.
static bool isConsecutiveLSLoc(SDValue Loc, EVT VT, LSBaseSDNode *Base, unsigned Bytes, int Dist, SelectionDAG &DAG)
static void StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG, SDValue Chain, const SmallVectorImpl< TailCallArgumentInfo > &TailCallArgs, SmallVectorImpl< SDValue > &MemOpChains, const SDLoc &dl)
StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
static cl::opt< bool > UseAbsoluteJumpTables("ppc-use-absolute-jumptables", cl::desc("use absolute jump tables on ppc"), cl::Hidden)
static void getMaxByValAlign(Type *Ty, Align &MaxAlign, Align MaxMaxAlign)
getMaxByValAlign - Helper for getByValTypeAlignment to determine the desired ByVal argument alignment...
static bool isConsecutiveLS(SDNode *N, LSBaseSDNode *Base, unsigned Bytes, int Dist, SelectionDAG &DAG)
static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize, unsigned LHSStart, unsigned RHSStart)
isVMerge - Common function, used to match vmrg* shuffles.
static void getLabelAccessInfo(bool IsPIC, const PPCSubtarget &Subtarget, unsigned &HiOpFlags, unsigned &LoOpFlags, const GlobalValue *GV=nullptr)
Return true if we should reference labels using a PICBase, set the HiOpFlags and LoOpFlags to the tar...
static void buildCallOperands(SmallVectorImpl< SDValue > &Ops, PPCTargetLowering::CallFlags CFlags, const SDLoc &dl, SelectionDAG &DAG, SmallVector< std::pair< unsigned, SDValue >, 8 > &RegsToPass, SDValue Glue, SDValue Chain, SDValue &Callee, int SPDiff, const PPCSubtarget &Subtarget)
static cl::opt< bool > DisableInnermostLoopAlign32("disable-ppc-innermost-loop-align32", cl::desc("don't always align innermost loop to 32 bytes on ppc"), cl::Hidden)
static bool usePartialVectorLoads(SDNode *N, const PPCSubtarget &ST)
Returns true if we should use a direct load into vector instruction (such as lxsd or lfd),...
static cl::opt< bool > DisableSCO("disable-ppc-sco", cl::desc("disable sibling call optimization on ppc"), cl::Hidden)
static void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain, const SDLoc &dl, int SPDiff, unsigned NumBytes, SDValue LROp, SDValue FPOp, SmallVectorImpl< TailCallArgumentInfo > &TailCallArguments)
static void fixupFuncForFI(SelectionDAG &DAG, int FrameIdx, EVT VT)
static cl::opt< bool > DisablePPCPreinc("disable-ppc-preinc", cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden)
static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags, unsigned PtrByteSize)
CalculateStackSlotSize - Calculates the size reserved for this argument on the stack.
static SDValue getSToVPermuted(SDValue OrigSToV, SelectionDAG &DAG)
static int CalculateTailCallSPDiff(SelectionDAG &DAG, bool isTailCall, unsigned ParamSize)
CalculateTailCallSPDiff - Get the amount the stack pointer has to be adjusted to accommodate the argu...
static void prepareIndirectCall(SelectionDAG &DAG, SDValue &Callee, SDValue &Glue, SDValue &Chain, const SDLoc &dl)
static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC, SelectionDAG &DAG)
static SDValue isScalarToVec(SDValue Op)
static SDValue widenVec(SelectionDAG &DAG, SDValue Vec, const SDLoc &dl)
static bool getVectorCompareInfo(SDValue Intrin, int &CompareOpc, bool &isDot, const PPCSubtarget &Subtarget)
getVectorCompareInfo - Given an intrinsic, return false if it is not a vector comparison.
static unsigned invertFMAOpcode(unsigned Opc)
static Instruction * callIntrinsic(IRBuilder<> &Builder, Intrinsic::ID Id)
static const SDValue * getNormalLoadInput(const SDValue &Op, bool &IsPermuted)
static int getEstimateRefinementSteps(EVT VT, const PPCSubtarget &Subtarget)
static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG, SDValue Chain, SDValue OldRetAddr, SDValue OldFP, int SPDiff, const SDLoc &dl)
EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to the appropriate stack sl...
static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt, EVT VT, SelectionDAG &DAG, const SDLoc &dl)
BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified amount.
static SDValue truncateScalarIntegerArg(ISD::ArgFlagsTy Flags, EVT ValVT, SelectionDAG &DAG, SDValue ArgValue, MVT LocVT, const SDLoc &dl)
static const TargetRegisterClass * getRegClassForSVT(MVT::SimpleValueType SVT, bool IsPPC64)
cl::opt< bool > ANDIGlueBug
static SDValue getOutputChainFromCallSeq(SDValue CallSeqStart)
static bool isIndirectCall(const SDValue &Callee, SelectionDAG &DAG, const PPCSubtarget &Subtarget, bool isPatchPoint)
static void prepareDescriptorIndirectCall(SelectionDAG &DAG, SDValue &Callee, SDValue &Glue, SDValue &Chain, SDValue CallSeqStart, const CallBase *CB, const SDLoc &dl, bool hasNest, const PPCSubtarget &Subtarget)
static bool isXXBRShuffleMaskHelper(ShuffleVectorSDNode *N, int Width)
static bool isSplatBV(SDValue Op)
static SDValue combineBVOfVecSExt(SDNode *N, SelectionDAG &DAG)
static cl::opt< bool > DisableILPPref("disable-ppc-ilp-pref", cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden)
static bool isNByteElemShuffleMask(ShuffleVectorSDNode *, unsigned, int)
Check that the mask is shuffling N byte elements.
static SDValue combineBVOfConsecutiveLoads(SDNode *N, SelectionDAG &DAG)
Reduce the number of loads when building a vector.
static bool isValidPCRelNode(SDValue N)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool isSplat(ArrayRef< Value * > VL)
#define STATISTIC(VARNAME, DESC)
This file describes how to lower LLVM code to machine code.
This defines the Use class.
static Optional< unsigned > getOpcode(ArrayRef< VPValue * > Values)
Returns the opcode of Values or ~0 if they do not all agree.
static bool contains(SmallPtrSetImpl< ConstantExpr * > &Cache, ConstantExpr *Expr, Constant *C)
static bool is64Bit(const char *name)
Class for arbitrary precision integers.
static APInt getAllOnesValue(unsigned numBits)
Get the all-ones value.
bool isPowerOf2() const
Check if this APInt's value is a power of two greater than zero.
static APInt getLowBitsSet(unsigned numBits, unsigned loBitsSet)
Get a value with low bits set.
static APInt getHighBitsSet(unsigned numBits, unsigned hiBitsSet)
Get a value with high bits set.
This class represents an incoming formal argument to a Function.
StringRef getValueAsString() const
Return the attribute's value as a string.
LLVM Basic Block Representation.
const Function * getParent() const
Return the enclosing method, or null if none.
The address of a basic block.
static BranchProbability getOne()
static BranchProbability getZero()
A "pseudo-class" with methods for operating on BUILD_VECTORs.
CCState - This class holds information needed while lowering arguments and return values.
CCValAssign - Represent assignment of one arg/retval to a location.
Register getLocReg() const
static CCValAssign getReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP)
static CCValAssign getCustomMem(unsigned ValNo, MVT ValVT, unsigned Offset, MVT LocVT, LocInfo HTP)
static CCValAssign getMem(unsigned ValNo, MVT ValVT, unsigned Offset, MVT LocVT, LocInfo HTP)
static CCValAssign getCustomReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP)
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
Function * getCalledFunction() const
Returns the function called, or null if this is an indirect function invocation.
CallingConv::ID getCallingConv() const
User::op_iterator arg_begin()
Return the iterator pointing to the beginning of the argument list.
bool isMustTailCall() const
Tests if this call site must be tail call optimized.
Value * getCalledOperand() const
User::op_iterator arg_end()
Return the iterator pointing to the end of the argument list.
unsigned arg_size() const
This class represents a function call, abstracting a target machine's calling convention.
ConstantFP - Floating Point Values [float, double].
static Constant * get(Type *Ty, double V)
This returns a ConstantFP, or a vector containing a splat of a ConstantFP, for the specified value in...
This is the shared class of boolean and integer constants.
static Constant * get(ArrayRef< Constant * > V)
This is an important base class in LLVM.
A parsed version of the target data layout string in and methods for querying it.
bool isLittleEndian() const
Layout endianness...
unsigned getLargestLegalIntTypeSizeInBits() const
Returns the size of largest legal integer type size, or 0 if none are set.
IntegerType * getIntPtrType(LLVMContext &C, unsigned AddressSpace=0) const
Returns an integer type with size at least as big as that of a pointer in the given address space.
Align getABITypeAlign(Type *Ty) const
Returns the minimum ABI-required alignment for the specified type.
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
bool hasOptSize() const
Optimize this function for size (-Os) or minimum size (-Oz).
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
bool hasMinSize() const
Optimize this function for minimum size (-Oz).
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
const Function & getFunction() const
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
const GlobalObject * getBaseObject() const
bool isDeclaration() const
Return true if the primary definition of this global value is outside of the current translation unit...
StringRef getSection() const
Module * getParent()
Get the module that this global value is contained inside of...
bool isStrongDefinitionForLinker() const
Returns true if this global's definition will be the one chosen by the linker.
const BasicBlock * getParent() const
bool hasAtomicLoad() const
Return true if this atomic instruction loads from memory.
static LLT scalar(unsigned SizeInBits)
Get a low-level scalar or aggregate "bag of bits".
This is an important class for using LLVM in a threaded context.
Base class for LoadSDNode and StoreSDNode.
This class is used to represent ISD::LOAD nodes.
const std::vector< LoopT * > & getSubLoops() const
Return the loops contained entirely within this loop.
unsigned getLoopDepth() const
Return the nesting level of this loop.
block_iterator block_end() const
block_iterator block_begin() const
Context object for machine code objects.
Base class for the full range of assembler expressions which are needed for parsing.
Wrapper class representing physical registers. Should be passed by value.
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
StringRef getSymbolTableName() const
void setRepresentedCsect(MCSectionXCOFF *C)
bool hasRepresentedCsectSet() const
TypeSize getScalarSizeInBits() const
static mvt_range fixedlen_vector_valuetypes()
@ INVALID_SIMPLE_VALUE_TYPE
bool isVector() const
Return true if this is a vector value type.
bool isInteger() const
Return true if this is an integer or a vector integer type.
static mvt_range integer_valuetypes()
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
TypeSize getStoreSize() const
Return the number of bytes overwritten by a store of the specified value type.
bool isScalarInteger() const
Return true if this is an integer, not including vectors.
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
static MVT getIntegerVT(unsigned BitWidth)
static mvt_range fp_valuetypes()
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
void setFrameAddressIsTaken(bool T)
void setReturnAddressIsTaken(bool s)
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
bool hasVAStart() const
Returns true if the function calls the llvm.va_start intrinsic.
int64_t getObjectOffset(int ObjectIdx) const
Return the assigned stack offset of the specified object from the incoming stack pointer.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, uint64_t s, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
MCSymbol * getPICBaseSymbol() const
getPICBaseSymbol - Return a function-local symbol to represent the PIC base.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Function & getFunction()
Return the LLVM function that this machine code represents.
MachineModuleInfo & getMMI() const
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Register addLiveIn(MCRegister PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
void insert(iterator MBBI, MachineBasicBlock *MBB)
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & addFrameIndex(int Idx) const
const MachineInstrBuilder & addRegMask(const uint32_t *Mask) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
const MachineInstrBuilder & cloneMemRefs(const MachineInstr &OtherMI) const
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
const MachineInstrBuilder & addDef(Register RegNo, unsigned Flags=0, unsigned SubReg=0) const
Add a virtual register definition operand.
Representation of each machine instruction.
@ EK_LabelDifference32
EK_LabelDifference32 - Each entry is the address of the block minus the address of the jump table.
A description of a memory reference used in the backend.
uint64_t getSize() const
Return the size in bytes of the memory reference.
Flags
Flags values. These may be or'd together.
@ MODereferenceable
The memory access is dereferenceable (i.e., doesn't trap).
@ MOLoad
The memory access reads data.
@ MOInvariant
The memory access always returns the same value (or traps).
@ MOStore
The memory access writes data.
Align getAlign() const
Return the minimum known alignment in bytes of the actual memory reference.
const MCContext & getContext() const
MachineOperand class - Representation of each machine instruction operand.
static MachineOperand CreateImm(int64_t Val)
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Register getLiveInVirtReg(MCRegister PReg) const
getLiveInVirtReg - If PReg is a live-in physical register, return the corresponding live-in physical ...
This SDNode is used for target intrinsics that touch memory and need an associated MachineMemOperand.
This is an abstract virtual class for memory operations.
const SDValue & getBasePtr() const
A Module instance is used to store all the information related to an LLVM module.
unsigned getTOCSaveOffset() const
getTOCSaveOffset - Return the previous frame offset to save the TOC register – 64-bit SVR4 ABI only.
unsigned getLinkageSize() const
getLinkageSize - Return the size of the PowerPC ABI linkage area.
unsigned getFramePointerSaveOffset() const
getFramePointerSaveOffset - Return the previous frame offset to save the frame pointer.
unsigned getReturnSaveOffset() const
getReturnSaveOffset - Return the previous frame offset to save the return address.
PPCFunctionInfo - This class is derived from MachineFunction private PowerPC target-specific informat...
void setVarArgsNumFPR(unsigned Num)
void setReturnAddrSaveIndex(int idx)
int getReturnAddrSaveIndex() const
unsigned getVarArgsNumFPR() const
int getFramePointerSaveIndex() const
void setVarArgsNumGPR(unsigned Num)
int getVarArgsFrameIndex() const
void setLRStoreRequired()
void setTailCallSPDelta(int size)
void setMinReservedArea(unsigned size)
unsigned getVarArgsNumGPR() const
unsigned getMinReservedArea() const
void setVarArgsStackOffset(int Offset)
void setVarArgsFrameIndex(int Index)
void addLiveInAttr(Register VReg, ISD::ArgFlagsTy Flags)
This function associates attributes for each live-in virtual register.
int getVarArgsStackOffset() const
void setFramePointerSaveIndex(int Idx)
bool useLongCalls() const
bool is32BitELFABI() const
unsigned descriptorTOCAnchorOffset() const
bool useSoftFloat() const
bool use64BitRegs() const
use64BitRegs - Return true if in 64-bit mode or if we should use 64-bit registers in 32-bit mode when...
bool allowsUnalignedFPAccess() const
const PPCFrameLowering * getFrameLowering() const override
bool needsSwapsForVSXMemOps() const
bool isPPC64() const
isPPC64 - Return true if we are generating code for 64-bit pointer mode.
bool needsTwoConstNR() const
bool isUsingPCRelativeCalls() const
bool usesFunctionDescriptors() const
True if the ABI is descriptor based.
MCRegister getEnvironmentPointerRegister() const
const PPCInstrInfo * getInstrInfo() const override
bool useCRBits() const
useCRBits - Return true if we should store and manipulate i1 values in the individual condition regis...
bool hasRecipPrec() const
bool hasInvariantFunctionDescriptors() const
unsigned getCPUDirective() const
getCPUDirective - Returns the -m directive specified for the cpu.
POPCNTDKind hasPOPCNTD() const
bool hasPrefixInstrs() const
bool hasPartwordAtomics() const
bool isLittleEndian() const
bool isTargetLinux() const
bool hasP9Altivec() const
MCRegister getTOCPointerRegister() const
MCRegister getStackPointerRegister() const
bool has64BitSupport() const
has64BitSupport - Return true if the selected CPU supports 64-bit instructions, regardless of whether...
bool is64BitELFABI() const
const PPCTargetMachine & getTargetMachine() const
bool isPredictableSelectIsExpensive() const
bool enableMachineScheduler() const override
Scheduling customization.
const PPCRegisterInfo * getRegisterInfo() const override
bool isGVIndirectSymbol(const GlobalValue *GV) const
True if the GV will be accessed via an indirect symbol.
unsigned descriptorEnvironmentPointerOffset() const
bool hasDirectMove() const
bool hasP8Altivec() const
MachineBasicBlock * emitEHSjLjLongJmp(MachineInstr &MI, MachineBasicBlock *MBB) const
unsigned getStackProbeSize(MachineFunction &MF) const
bool isTruncateFree(Type *Ty1, Type *Ty2) const override
isTruncateFree - Return true if it's free to truncate a value of type Ty1 to type Ty2.
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
bool isFPExtFree(EVT DestVT, EVT SrcVT) const override
Return true if an fpext operation is free (for instance, because single-precision floating-point numb...
MachineBasicBlock * emitEHSjLjSetJmp(MachineInstr &MI, MachineBasicBlock *MBB) const
const char * getTargetNodeName(unsigned Opcode) const override
getTargetNodeName() - This method returns the name of a target specific DAG node.
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
MachineBasicBlock * emitProbedAlloca(MachineInstr &MI, MachineBasicBlock *MBB) const
bool isZExtFree(SDValue Val, EVT VT2) const override
Return true if zero-extending the specific node Val to type VT2 is free (either because it's implicit...
MachineBasicBlock * EmitPartwordAtomicBinary(MachineInstr &MI, MachineBasicBlock *MBB, bool is8bit, unsigned Opcode, unsigned CmpOpcode=0, unsigned CmpPred=0) const
SDValue getNegatedExpression(SDValue Op, SelectionDAG &DAG, bool LegalOps, bool OptForSize, NegatibleCost &Cost, unsigned Depth=0) const override
Return the newly negated expression if the cost is not expensive and set the cost in Cost to indicate...
bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base, SelectionDAG &DAG, MaybeAlign EncodingAlignment) const
SelectAddressRegImm - Returns true if the address N can be represented by a base register plus a sign...
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, MachineFunction &MF, unsigned Intrinsic) const override
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
SDValue expandVSXLoadForLE(SDNode *N, DAGCombinerInfo &DCI) const
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
ReplaceNodeResults - Replace the results of node with an illegal result type with new values built ou...
unsigned getByValTypeAlignment(Type *Ty, const DataLayout &DL) const override
getByValTypeAlignment - Return the desired alignment for ByVal aggregate function arguments in the ca...
MachineBasicBlock * EmitAtomicBinary(MachineInstr &MI, MachineBasicBlock *MBB, unsigned AtomicSize, unsigned BinOpcode, unsigned CmpOpcode=0, unsigned CmpPred=0) const
SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, SmallVectorImpl< SDNode * > &Created) const override
Targets may override this function to provide custom SDIV lowering for power-of-2 denominators.
void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index, SelectionDAG &DAG) const
SelectAddressRegRegOnly - Given the specified addressed, force it to be represented as an indexed [r+...
bool useSoftFloat() const override
SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const override
Returns relocation base for the given PIC jumptable.
void insertSSPDeclarations(Module &M) const override
Inserts necessary declarations for SSP (stack protection) purpose.
ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const override
Examine constraint string and operand type and determine a weight value.
bool isMulhCheaperThanMulShift(EVT Type) const override
isMulhCheaperThanMulShift - Return true if a mulh[s|u] node for a specific type is cheaper than a mul...
bool enableAggressiveFMAFusion(EVT VT) const override
Return true if target always beneficiates from combining into FMA for a given value type.
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.
Instruction * emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst, AtomicOrdering Ord) const override
Inserts in the IR a target-specific intrinsic specifying a fence.
unsigned getJumpTableEncoding() const override
Return the entry encoding for a jump table in the current function.
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target...
bool preferIncOfAddToSubOfNot(EVT VT) const override
These two forms are equivalent: sub y, (xor x, -1) add (add x, 1), y The variant with two add's is IR...
bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const override
Returns true if it is beneficial to convert a load of a constant to just the constant itself.
const MCPhysReg * getScratchRegisters(CallingConv::ID CC) const override
Returns a 0 terminated array of registers that can be safely used as scratch registers.
bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
getPreIndexedAddressParts - returns true by value, base pointer and offset pointer and addressing mod...
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
LowerAsmOperandForConstraint - Lower the specified operand into the Ops vector.
bool isProfitableToHoist(Instruction *I) const override
isProfitableToHoist - Check if it is profitable to hoist instruction I to its dominator block.
bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override
Returns true if the target can instruction select the specified FP immediate natively.
ConstraintType getConstraintType(StringRef Constraint) const override
getConstraintType - Given a constraint, return the type of constraint it is for this target.
const MCExpr * getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, MCContext &Ctx) const override
This returns the relocation base for the given PIC jumptable, the same as getPICJumpTableRelocBase,...
EVT getOptimalMemOpType(const MemOp &Op, const AttributeList &FuncAttributes) const override
It returns EVT::Other if the type should be determined using generic target-independent logic.
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace, unsigned Align=1, MachineMemOperand::Flags Flags=MachineMemOperand::MONone, bool *Fast=nullptr) const override
Is unaligned memory access allowed for the given type, and is it fast relative to software emulation.
SDValue expandVSXStoreForLE(SDNode *N, DAGCombinerInfo &DCI) const
bool useLoadStackGuardNode() const override
Override to support customized stack guard loading.
bool hasInlineStackProbe(MachineFunction &MF) const override
PPCTargetLowering(const PPCTargetMachine &TM, const PPCSubtarget &STI)
bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index, SelectionDAG &DAG, MaybeAlign EncodingAlignment=None) const
SelectAddressRegReg - Given the specified addressed, check to see if it can be more efficiently repre...
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT VT) const override
isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster than a pair of fmul and fadd i...
bool shouldExpandBuildVectorWithShuffles(EVT VT, unsigned DefinedValues) const override
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
Register getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
bool isJumpTableRelative() const override
Register getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
LowerOperation - Provide custom lowering hooks for some operations.
bool SelectAddressPCRel(SDValue N, SDValue &Base) const
SelectAddressPCRel - Represent the specified address as pc relative to be represented as [pc+imm].
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override
getSetCCResultType - Return the ISD::SETCC ValueType
Instruction * emitTrailingFence(IRBuilder<> &Builder, Instruction *Inst, AtomicOrdering Ord) const override
bool SelectAddressEVXRegReg(SDValue N, SDValue &Base, SDValue &Index, SelectionDAG &DAG) const
SelectAddressEVXRegReg - Given the specified addressed, check to see if it can be more efficiently re...
bool isLegalICmpImmediate(int64_t Imm) const override
isLegalICmpImmediate - Return true if the specified immediate is legal icmp immediate,...
bool isAccessedAsGotIndirect(SDValue N) const
Align getPrefLoopAlignment(MachineLoop *ML) const override
Return the preferred loop alignment.
FastISel * createFastISel(FunctionLoweringInfo &FuncInfo, const TargetLibraryInfo *LibInfo) const override
createFastISel - This method returns a target-specific FastISel object, or null if the target does no...
bool isLegalAddImmediate(int64_t Imm) const override
isLegalAddImmediate - Return true if the specified immediate is legal add immediate,...
Common code between 32-bit and 64-bit PowerPC targets.
Wrapper class representing virtual and physical registers.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
This class provides iterator support for SDUse operands that use a specific SDNode.
Represents one node in the SelectionDAG.
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
bool hasOneUse() const
Return true if there is exactly one use of this node.
const SDValue & getOperand(unsigned Num) const
use_iterator use_begin() const
Provide iteration support to walk over all uses of an SDNode.
bool isPredecessorOf(const SDNode *N) const
Return true if this node is a predecessor of N.
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
const SDNodeFlags getFlags() const
static use_iterator use_end()
Represents a use of a SDNode.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
SDNode * getNode() const
get the SDNode which holds the desired result
bool hasOneUse() const
Return true if there is exactly one node using value ResNo of Node.
SDValue getValue(unsigned R) const
EVT getValueType() const
Return the ValueType of the referenced return value.
const SDValue & getOperand(unsigned i) const
MVT getSimpleValueType() const
Return the simple ValueType of the referenced return value.
unsigned getOpcode() const
unsigned getNumOperands() const
static SectionKind getMetadata()
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned TargetFlags=0)
SDValue getStackArgumentTokenFactor(SDValue Chain)
Compute a TokenFactor to force all the incoming stack arguments to be loaded from the stack.
const TargetSubtargetInfo & getSubtarget() const
SDValue getMergeValues(ArrayRef< SDValue > Ops, const SDLoc &dl)
Create a MERGE_VALUES node from the given operands.
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
MachineSDNode * getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT)
These are used for target selectors to create a new node with specified return type(s),...
SDValue getSetCC(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond, SDValue Chain=SDValue(), bool IsSignaling=false)
Helper function to make it easier to build SetCC's if you just have an ISD::CondCode instead of an SD...
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, MaybeAlign Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands,...
SDValue getConstantPool(const Constant *C, EVT VT, MaybeAlign Align=None, int Offs=0, bool isT=false, unsigned TargetFlags=0)
SDValue getConstantFP(double Val, const SDLoc &DL, EVT VT, bool isTarget=false)
Create a ConstantFPSDNode wrapping a constant value.
SDValue getTargetConstantPool(const Constant *C, EVT VT, MaybeAlign Align=None, int Offset=0, unsigned TargetFlags=0)
Align getEVTAlign(EVT MemoryVT) const
Compute the default alignment value for the given type.
void addNoMergeSiteInfo(const SDNode *Node, bool NoMerge)
const TargetLowering & getTargetLoweringInfo() const
static constexpr unsigned MaxRecursionDepth
SDValue getTargetJumpTable(int JTI, EVT VT, unsigned TargetFlags=0)
SDValue getUNDEF(EVT VT)
Return an UNDEF node. UNDEF does not have a useful SDLoc.
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd).
SDValue getBuildVector(EVT VT, const SDLoc &DL, ArrayRef< SDValue > Ops)
Return an ISD::BUILD_VECTOR node.
bool isSplatValue(SDValue V, const APInt &DemandedElts, APInt &UndefElts)
Test whether V has a splatted value for all the demanded elements.
SDValue getBitcast(EVT VT, SDValue V)
Return a bitcast using the SDLoc of the value operand, and casting to the provided type.
const DataLayout & getDataLayout() const
SDValue getTargetFrameIndex(int FI, EVT VT)
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
SDValue getTruncStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, EVT SVT, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
void ReplaceAllUsesWith(SDValue From, SDValue To)
Modify anything using 'From' to use 'To' instead.
SDValue getCommutedVectorShuffle(const ShuffleVectorSDNode &SV)
Returns an ISD::VECTOR_SHUFFLE node semantically equivalent to the shuffle node in input but with swa...
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL)
Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside ...
SDValue getRegister(unsigned Reg, EVT VT)
SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo)
SDValue getSExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either sign-extending or trunca...
SDValue getIndexedStore(SDValue OrigStore, const SDLoc &dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM)
SDValue getExternalSymbol(const char *Sym, EVT VT)
const TargetMachine & getTarget() const
SDValue getAnyExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either any-extending or truncat...
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
SDValue getSelectCC(const SDLoc &DL, SDValue LHS, SDValue RHS, SDValue True, SDValue False, ISD::CondCode Cond)
Helper function to make it easier to build SelectCC's if you just have an ISD::CondCode instead of an...
SDValue getMemIntrinsicNode(unsigned Opcode, const SDLoc &dl, SDVTList VTList, ArrayRef< SDValue > Ops, EVT MemVT, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags Flags=MachineMemOperand::MOLoad|MachineMemOperand::MOStore, uint64_t Size=0, const AAMDNodes &AAInfo=AAMDNodes())
Creates a MemIntrinsicNode that may produce a result and takes a list of operands.
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
SDValue getValueType(EVT)
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
unsigned ComputeNumSignBits(SDValue Op, unsigned Depth=0) const
Return the number of times the sign bit of the register is replicated into the other bits.
SDValue getTargetBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, unsigned TargetFlags=0)
bool isBaseWithConstantOffset(SDValue Op) const
Return true if the specified operand is an ISD::ADD with a ConstantSDNode on the right-hand side,...
SDValue getVectorIdxConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
void ReplaceAllUsesOfValueWith(SDValue From, SDValue To)
Replace any uses of From with To, leaving uses of other values produced by From.getNode() alone.
MachineFunction & getMachineFunction() const
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
SDValue getSplatBuildVector(EVT VT, const SDLoc &DL, SDValue Op)
Return a splat ISD::BUILD_VECTOR node, consisting of Op splatted to all elements.
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
KnownBits computeKnownBits(SDValue Op, unsigned Depth=0) const
Determine which bits of Op are known to be either zero or one and return them in Known.
SDValue getRegisterMask(const uint32_t *RegMask)
SDValue getZExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either zero-extending or trunca...
bool MaskedValueIsZero(SDValue Op, const APInt &Mask, unsigned Depth=0) const
Return true if 'Op & Mask' is known to be zero.
LLVMContext * getContext() const
SDValue getExtLoad(ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, MaybeAlign Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned TargetFlags=0)
SDValue getMCSymbol(MCSymbol *Sym, EVT VT)
SDValue CreateStackTemporary(TypeSize Bytes, Align Alignment)
Create a stack temporary based on the size in bytes and the alignment.
SDNode * UpdateNodeOperands(SDNode *N, SDValue Op)
Mutate the specified node in-place to have the specified operands.
SDValue getIndexedLoad(SDValue OrigLoad, const SDLoc &dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM)
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
SDValue getObjectPtrOffset(const SDLoc &SL, SDValue Ptr, int64_t Offset)
Create an add instruction with appropriate flags when used for addressing some offset of an object.
SDValue getVectorShuffle(EVT VT, const SDLoc &dl, SDValue N1, SDValue N2, ArrayRef< int > Mask)
Return an ISD::VECTOR_SHUFFLE node.
This SDNode is used to implement the code generator support for the llvm IR shufflevector instruction...
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StackOffset is a wrapper around scalable and non-scalable offsets and is used in several functions su...
This class is used to represent ISD::STORE nodes.
StringRef - Represent a constant reference to a string, i.e.
std::enable_if_t< std::numeric_limits< T >::is_signed, bool > getAsInteger(unsigned Radix, T &Result) const
Parse the current string as an integer of the specified radix.
LLVM_NODISCARD size_t size() const
size - Get the string size.
LLVM_NODISCARD const char * data() const
data - Get a pointer to the start of the string (which may not be null terminated).
Class to represent struct types.
Information about stack frame layout on the target.
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
TargetInstrInfo - Interface to description of machine instruction set.
Provides information about what library functions are available for the current target.
void setBooleanVectorContents(BooleanContent Ty)
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
void setTargetDAGCombine(ISD::NodeType NT)
Targets should invoke this method for each target independent node that they want to provide a custom...
bool PredictableSelectIsExpensive
Tells the code generator that select is more expensive than a branch if the branch is usually predict...
EVT getValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the EVT corresponding to this LLVM type.
virtual bool shouldExpandBuildVectorWithShuffles(EVT, unsigned DefinedValues) const
unsigned MaxStoresPerMemcpyOptSize
Likewise for functions with the OptSize attribute.
MachineBasicBlock * emitPatchPoint(MachineInstr &MI, MachineBasicBlock *MBB) const
Replace/modify any TargetFrameIndex operands with a targte-dependent sequence of memory operands that...
virtual const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent=false) const
Return the register class that should be used for the specified value type.
void setIndexedStoreAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed store does or does not work with the specified type and indicate ...
void setMinStackArgumentAlignment(Align Alignment)
Set the minimum stack alignment of an argument.
const TargetMachine & getTargetMachine() const
unsigned MaxLoadsPerMemcmp
Specify maximum number of load instructions per memcmp call.
virtual bool isZExtFree(Type *FromTy, Type *ToTy) const
Return true if any actual instruction that defines a value of type FromTy implicitly zero-extends the...
bool isOperationLegalOrCustom(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target or can be made legal with custom lower...
virtual bool isMulhCheaperThanMulShift(EVT Type) const
Return true if a mulh[s|u] node for a specific type is cheaper than a multiply followed by a shift.
void setPrefLoopAlignment(Align Alignment)
Set the target's preferred loop alignment.
void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits)
Set the maximum atomic operation size supported by the backend.
virtual Align getPrefLoopAlignment(MachineLoop *ML=nullptr) const
Return the preferred loop alignment.
Sched::Preference getSchedulingPreference() const
Return target scheduling preference.
void setMinFunctionAlignment(Align Alignment)
Set the target's minimum function alignment.
bool isOperationCustom(unsigned Op, EVT VT) const
Return true if the operation uses custom lowering, regardless of whether the type is legal or not.
void setCondCodeAction(ISD::CondCode CC, MVT VT, LegalizeAction Action)
Indicate that the specified condition code is or isn't supported on the target and indicate what to d...
unsigned MaxStoresPerMemsetOptSize
Likewise for functions with the OptSize attribute.
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
unsigned MaxStoresPerMemmove
Specify maximum number of store instructions per memmove call.
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose.
EVT getShiftAmountTy(EVT LHSTy, const DataLayout &DL, bool LegalTypes=true) const
unsigned MaxStoresPerMemmoveOptSize
Likewise for functions with the OptSize attribute.
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type.
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
virtual bool isJumpTableRelative() const
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
void setLibcallName(RTLIB::Libcall Call, const char *Name)
Rename the default libcall routine name for the specified libcall.
void setPrefFunctionAlignment(Align Alignment)
Set the target's preferred function alignment.
bool isOperationLegal(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target.
unsigned MaxStoresPerMemset
Specify maximum number of store instructions per memset call.
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
@ ZeroOrOneBooleanContent
@ ZeroOrNegativeOneBooleanContent
unsigned MaxLoadsPerMemcmpOptSize
Likewise for functions with the OptSize attribute.
void setStackPointerRegisterToSaveRestore(Register R)
If set to a physical register, this specifies the register that llvm.savestack/llvm....
void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)
If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/...
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
NegatibleCost
Enum that specifies when a float negation is beneficial.
std::vector< ArgListEntry > ArgListTy
void setHasMultipleConditionRegisters(bool hasManyRegs=true)
Tells the code generator that the target has multiple (allocatable) condition registers that can be u...
unsigned MaxStoresPerMemcpy
Specify maximum number of store instructions per memcpy call.
void setSchedulingPreference(Sched::Preference Pref)
Specify the target scheduling preference.
virtual void insertSSPDeclarations(Module &M) const
Inserts necessary declarations for SSP (stack protection) purpose.
void setJumpIsExpensive(bool isExpensive=true)
Tells the code generator not to expand logic operations on comparison predicates into separate sequen...
void setIndexedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action)
Indicate that the specified indexed load does or does not work with the specified type and indicate w...
static XCOFF::StorageClass getStorageClassForGlobal(const GlobalObject *GO)
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
virtual const MCExpr * getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, MCContext &Ctx) const
This returns the relocation base for the given PIC jumptable, the same as getPICJumpTableRelocBase,...
SDValue lowerCmpEqZeroToCtlzSrl(SDValue Op, SelectionDAG &DAG) const
virtual bool useLoadStackGuardNode() const
If this function returns true, SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering ...
SDValue getCheaperNegatedExpression(SDValue Op, SelectionDAG &DAG, bool LegalOps, bool OptForSize, unsigned Depth=0) const
This is the helper function to return the newly negated expression only when the cost is cheaper.
virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const
Lower the specified operand into the Ops vector.
virtual ConstraintType getConstraintType(StringRef Constraint) const
Given a constraint, return the type of constraint it is for this target.
virtual SDValue LowerToTLSEmulatedModel(const GlobalAddressSDNode *GA, SelectionDAG &DAG) const
Lower TLS global address SDNode for target independent emulated TLS model.
std::pair< SDValue, SDValue > LowerCallTo(CallLoweringInfo &CLI) const
This function lowers an abstract call to a function into an actual call.
bool isPositionIndependent() const
virtual SDValue getNegatedExpression(SDValue Op, SelectionDAG &DAG, bool LegalOps, bool OptForSize, NegatibleCost &Cost, unsigned Depth=0) const
Return the newly negated expression if the cost is not expensive and set the cost in Cost to indicate...
virtual ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const
Examine constraint string and operand type and determine a weight value.
virtual SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const
Returns relocation base for the given PIC jumptable.
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
bool verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const
virtual bool isGAPlusOffset(SDNode *N, const GlobalValue *&GA, int64_t &Offset) const
Returns true (and the GlobalValue and the offset) if the node is a GlobalAddress + offset.
virtual unsigned getJumpTableEncoding() const
Return the entry encoding for a jump table in the current function.
Primary interface to the complete machine description for the target machine.
bool useEmulatedTLS() const
Returns true if this target uses emulated TLS.
Reloc::Model getRelocationModel() const
Returns the code generation relocation model.
CodeModel::Model getCodeModel() const
Returns the code model.
bool shouldAssumeDSOLocal(const Module &M, const GlobalValue *GV) const
unsigned UnsafeFPMath
UnsafeFPMath - This flag is enabled when the -enable-unsafe-fp-math flag is specified on the command ...
unsigned NoInfsFPMath
NoInfsFPMath - This flag is enabled when the -enable-no-infs-fp-math flag is specified on the command...
unsigned NoSignedZerosFPMath
NoSignedZerosFPMath - This flag is enabled when the -enable-no-signed-zeros-fp-math is specified on t...
unsigned NoNaNsFPMath
NoNaNsFPMath - This flag is enabled when the -enable-no-nans-fp-math flag is specified on the command...
unsigned GuaranteedTailCallOpt
GuaranteedTailCallOpt - This flag is enabled when -tailcallopt is specified on the commandline.
FPOpFusion::FPOpFusionMode AllowFPOpFusion
AllowFPOpFusion - This flag is set by the -fuse-fp-ops=xxx option.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Target - Wrapper for Target specific information.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
The instances of the Type class are immutable: once they are created, they are never changed.
bool isVectorTy() const
True if this is an instance of VectorType.
bool isFloatTy() const
Return true if this is 'float', a 32-bit IEEE fp type.
@ FloatTyID
32-bit floating point type
@ DoubleTyID
64-bit floating point type
@ FP128TyID
128-bit floating point type (112-bit significand)
static Type * getVoidTy(LLVMContext &C)
bool isDoubleTy() const
Return true if this is 'double', a 64-bit IEEE fp type.
bool isIntegerTy() const
True if this is an instance of IntegerType.
static Type * getFloatTy(LLVMContext &C)
static UndefValue * get(Type *T)
Static factory methods - Return an 'undef' object of the specified type.
Value * getOperand(unsigned i) const
unsigned getNumOperands() const
LLVM Value Representation.
Type * getType() const
All values are typed, get the type of this value.
StringRef getName() const
Return a constant reference to the value's name.
Implementation for an ilist node.
ilist_node_impl()=default
self_iterator getIterator()
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
@ Fast
Fast - This calling convention attempts to make calls as fast as possible (e.g.
@ C
C - The default llvm calling convention, compatible with C.
bool isNON_EXTLoad(const SDNode *N)
Returns true if the specified node is a non-extending load.
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
@ SETCC
SetCC operator - This evaluates to a true value iff the condition is true.
@ MERGE_VALUES
MERGE_VALUES - This node takes multiple discrete operands and returns them all as its individual resu...
@ STACKRESTORE
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain.
@ STACKSAVE
STACKSAVE - STACKSAVE has one operand, an input chain.
@ FLT_ROUNDS_
FLT_ROUNDS_ - Returns current rounding mode: -1 Undefined 0 Round to 0 1 Round to nearest 2 Round to ...
@ EH_SJLJ_LONGJMP
OUTCHAIN = EH_SJLJ_LONGJMP(INCHAIN, buffer) This corresponds to the eh.sjlj.longjmp intrinsic.
@ FGETSIGN
INT = FGETSIGN(FP) - Return the sign bit of the specified floating point value as an integer 0/1 valu...
@ SMUL_LOHI
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
@ BSWAP
Byte Swap and Counting operators.
@ VAEND
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE.
@ ATOMIC_STORE
OUTCHAIN = ATOMIC_STORE(INCHAIN, ptr, val) This corresponds to "store atomic" instruction.
@ ADDC
Carry-setting nodes for multiple precision addition and subtraction.
@ ADD
Simple integer binary arithmetic operators.
@ LOAD
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
@ FMA
FMA - Perform a * b + c with no intermediate rounding step.
@ INTRINSIC_VOID
OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) This node represents a target intrin...
@ SINT_TO_FP
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
@ CONCAT_VECTORS
CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of vector type with the same length ...
@ FADD
Simple binary floating point operators.
@ ABS
ABS - Determine the unsigned absolute value of a signed integer value of the same bitwidth.
@ SDIVREM
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
@ FP16_TO_FP
FP16_TO_FP, FP_TO_FP16 - These operators are used to perform promotions and truncation for half-preci...
@ BITCAST
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
@ BUILD_PAIR
BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
@ INIT_TRAMPOLINE
INIT_TRAMPOLINE - This corresponds to the init_trampoline intrinsic.
@ STRICT_FSQRT
Constrained versions of libm-equivalent floating point intrinsics.
@ SIGN_EXTEND
Conversion operators.
@ SCALAR_TO_VECTOR
SCALAR_TO_VECTOR(VAL) - This represents the operation of loading a scalar value into element 0 of the...
@ BR
Control flow instructions. These all have token chains.
@ PREFETCH
PREFETCH - This corresponds to a prefetch intrinsic.
@ FSINCOS
FSINCOS - Compute both fsin and fcos as a single operation.
@ FNEG
Perform various unary floating-point operations inspired by libm.
@ BR_CC
BR_CC - Conditional branch.
@ BR_JT
BR_JT - Jumptable branch.
@ SSUBSAT
RESULT = [US]SUBSAT(LHS, RHS) - Perform saturation subtraction on 2 integers with the same bit width ...
@ SELECT
Select(COND, TRUEVAL, FALSEVAL).
@ ATOMIC_LOAD
Val, OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr) This corresponds to "load atomic" instruction.
@ EXTRACT_ELEMENT
EXTRACT_ELEMENT - This is used to get the lower or upper (determined by a Constant,...
@ VACOPY
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer,...
@ TargetGlobalAddress
TargetGlobalAddress - Like GlobalAddress, but the DAG does no folding or anything else with this node...
@ MULHU
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
@ SHL
Shift and rotation operations.
@ VECTOR_SHUFFLE
VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.
@ EXTRACT_SUBVECTOR
EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR.
@ FMINNUM_IEEE
FMINNUM_IEEE/FMAXNUM_IEEE - Perform floating-point minimum or maximum on two values,...
@ EXTRACT_VECTOR_ELT
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
@ SELECT_CC
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
@ ATOMIC_CMP_SWAP
Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) For double-word atomic operations: ValLo,...
@ FMINNUM
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
@ DYNAMIC_STACKALLOC
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary.
@ SIGN_EXTEND_INREG
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
@ SMIN
[US]{MIN/MAX} - Binary minimum or maximum or signed or unsigned integers.
@ FP_EXTEND
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
@ VSELECT
Select with a vector condition (op #0) and two vector operands (ops #1 and #2), returning a vector re...
@ STRICT_SINT_TO_FP
STRICT_[US]INT_TO_FP - Convert a signed or unsigned integer to a floating point value.
@ EH_DWARF_CFA
EH_DWARF_CFA - This node represents the pointer to the DWARF Canonical Frame Address (CFA),...
@ FRAMEADDR
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG.
@ STRICT_FP_ROUND
X = STRICT_FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision ...
@ STRICT_FP_TO_SINT
STRICT_FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
@ FP_TO_SINT
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
@ READCYCLECOUNTER
READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic.
@ STRICT_FP_EXTEND
X = STRICT_FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
@ AND
Bitwise operators - logical and, logical or, logical xor.
@ TRAP
TRAP - Trapping instruction.
@ INTRINSIC_WO_CHAIN
RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic fun...
@ ADDE
Carry-using nodes for multiple precision addition and subtraction.
@ STRICT_FADD
Constrained versions of the binary floating point operators.
@ INSERT_VECTOR_ELT
INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL.
@ TokenFactor
TokenFactor - This node takes multiple tokens as input and produces a single token result.
@ FP_ROUND
X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision of the ...
@ ZERO_EXTEND_VECTOR_INREG
ZERO_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register zero-extension of the low ...
@ EH_SJLJ_SETJMP
RESULT, OUTCHAIN = EH_SJLJ_SETJMP(INCHAIN, buffer) This corresponds to the eh.sjlj....
@ TRUNCATE
TRUNCATE - Completely drop the high bits.
@ VAARG
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
@ BRCOND
BRCOND - Conditional branch.
@ SHL_PARTS
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations.
@ AssertSext
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
@ FCOPYSIGN
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
@ SADDSAT
RESULT = [US]ADDSAT(LHS, RHS) - Perform saturation addition on 2 integers with the same bit width (W)...
@ CALLSEQ_START
CALLSEQ_START/CALLSEQ_END - These operators mark the beginning and end of a call sequence,...
@ GET_DYNAMIC_AREA_OFFSET
GET_DYNAMIC_AREA_OFFSET - get offset from native SP to the address of the most recent dynamic alloca.
@ ADJUST_TRAMPOLINE
ADJUST_TRAMPOLINE - This corresponds to the adjust_trampoline intrinsic.
@ INTRINSIC_W_CHAIN
RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) This node represents a target in...
@ BUILD_VECTOR
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a fixed-width vector with the specified,...
bool isNormalStore(const SDNode *N)
Returns true if the specified node is a non-truncating and unindexed store.
bool isEXTLoad(const SDNode *N)
Returns true if the specified node is a EXTLOAD.
bool isBuildVectorAllZeros(const SDNode *N)
Return true if the specified node is a BUILD_VECTOR where all of the elements are 0 or undef.
bool isSignedIntSetCC(CondCode Code)
Return true if this is a setcc instruction that performs a signed comparison when used with integer o...
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
bool isUnsignedIntSetCC(CondCode Code)
Return true if this is a setcc instruction that performs an unsigned comparison when used with intege...
bool isNormalLoad(const SDNode *N)
Returns true if the specified node is a non-extending and unindexed load.
Function * getDeclaration(Module *M, ID id, ArrayRef< Type * > Tys=None)
Create or insert an LLVM Function declaration for an intrinsic, and return it.
@ Bitcast
Perform the operation on a different, but equivalently sized type.
Flag
These should be considered private to the implementation of the MCInstrDesc class.
@ MO_PCREL_FLAG
MO_PCREL_FLAG - If this bit is set, the symbol reference is relative to the current instruction addre...
@ MO_GOT_FLAG
MO_GOT_FLAG - If this bit is set the symbol reference is to be computed via the GOT.
@ MO_PLT
On a symbol operand "FOO", this indicates that the reference is actually to "FOO@plt".
@ MO_LO
MO_LO, MO_HA - lo16(symbol) and ha16(symbol)
@ MO_PIC_FLAG
MO_PIC_FLAG - If this bit is set, the symbol reference is relative to the function's picbase,...
@ QBFLT
QBFLT = Access the underlying QPX floating-point boolean representation.
@ FCTIDUZ
Newer FCTI[D,W]UZ floating-point-to-integer conversion instructions for unsigned integers with round ...
@ ADDI_TLSGD_L_ADDR
G8RC = ADDI_TLSGD_L_ADDR G8RReg, Symbol, Symbol - Op that combines ADDI_TLSGD_L and GET_TLS_ADDR unti...
@ DYNALLOC
The following two target-specific nodes are used for calls through function pointers in the 64-bit SV...
@ COND_BRANCH
CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This corresponds to the COND_BRANCH pseudo ...
@ QVGPCI
QVGPCI = This corresponds to the QPX qvgpci instruction.
@ VABSD
An SDNode for Power9 vector absolute value difference.
@ STORE_VEC_BE
CHAIN = STORE_VEC_BE CHAIN, VSRC, Ptr - Occurs only for little endian.
@ BDNZ
CHAIN = BDNZ CHAIN, DESTBB - These are used to create counter-based loops.
@ MTVSRZ
Direct move from a GPR to a VSX register (zero)
@ SRL
These nodes represent PPC shifts.
@ VECINSERT
VECINSERT - The PPC vector insert instruction.
@ QVFPERM
QVFPERM = This corresponds to the QPX qvfperm instruction.
@ LXSIZX
GPRC, CHAIN = LXSIZX, CHAIN, Ptr, ByteWidth - This is a load of an integer smaller than 64 bits into ...
@ FNMSUB
FNMSUB - Negated multiply-subtract instruction.
@ RFEBB
CHAIN = RFEBB CHAIN, State - Return from event-based branch.
@ VCMPo
RESVEC, OUTFLAG = VCMPo(LHS, RHS, OPC) - Represents one of the altivec VCMP*o instructions.
@ FCTIDZ
FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64 operand, producing an f64 value...
@ SC
CHAIN = SC CHAIN, Imm128 - System call.
@ GET_TLS_ADDR
x3 = GET_TLS_ADDR x3, Symbol - For the general-dynamic TLS model, produces a call to __tls_get_addr(s...
@ FP_TO_UINT_IN_VSR
Floating-point-to-interger conversion instructions.
@ XXSPLTI32DX
XXSPLTI32DX - The PPC XXSPLTI32DX instruction.
@ ANDI_rec_1_EQ_BIT
i1 = ANDI_rec_1_[EQ|GT]_BIT(i32 or i64 x) - Represents the result of the eq or gt bit of CR0 after ex...
@ FRE
Reciprocal estimate instructions (unary FP ops).
@ ADDIS_GOT_TPREL_HA
G8RC = ADDIS_GOT_TPREL_HA x2, Symbol - Used by the initial-exec TLS model, produces an ADDIS8 instruc...
@ CLRBHRB
CHAIN = CLRBHRB CHAIN - Clear branch history rolling buffer.
@ SINT_VEC_TO_FP
Extract a subvector from signed integer vector and convert to FP.
@ EXTRACT_SPE
Extract SPE register component, second argument is high or low.
@ XXSWAPD
VSRC, CHAIN = XXSWAPD CHAIN, VSRC - Occurs only for little endian.
@ ADDI_TLSLD_L_ADDR
G8RC = ADDI_TLSLD_L_ADDR G8RReg, Symbol, Symbol - Op that combines ADDI_TLSLD_L and GET_TLSLD_ADDR un...
@ ATOMIC_CMP_SWAP_8
ATOMIC_CMP_SWAP - the exact same as the target-independent nodes except they ensure that the compare ...
@ ST_VSR_SCAL_INT
Store scalar integers from VSR.
@ VCMP
RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP* instructions.
@ BCTRL
CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a BCTRL instruction.
@ BUILD_SPE64
BUILD_SPE64 and EXTRACT_SPE are analogous to BUILD_PAIR and EXTRACT_ELEMENT but take f64 arguments in...
@ LFIWZX
GPRC, CHAIN = LFIWZX CHAIN, Ptr - This is a floating-point load which zero-extends from a 32-bit inte...
@ SCALAR_TO_VECTOR_PERMUTED
PowerPC instructions that have SCALAR_TO_VECTOR semantics tend to place the value into the least sign...
@ STXSIX
STXSIX - The STXSI[bh]X instruction.
@ MAT_PCREL_ADDR
MAT_PCREL_ADDR = Materialize a PC Relative address.
@ MFOCRF
R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction.
@ XXSPLT
XXSPLT - The PPC VSX splat instructions.
@ TOC_ENTRY
GPRC = TOC_ENTRY GA, TOC Loads the entry for GA from the TOC, where the TOC base is given by the last...
@ XXPERMDI
XXPERMDI - The PPC XXPERMDI instruction.
@ ADDIS_DTPREL_HA
G8RC = ADDIS_DTPREL_HA x3, Symbol - For the local-dynamic TLS model, produces an ADDIS8 instruction t...
@ ADD_TLS
G8RC = ADD_TLS G8RReg, Symbol - Used by the initial-exec TLS model, produces an ADD instruction that ...
@ QVLFSb
QBRC, CHAIN = QVLFSb CHAIN, Ptr The 4xf32 load used for v4i1 constants.
@ MTVSRA
Direct move from a GPR to a VSX register (algebraic)
@ VADD_SPLAT
VRRC = VADD_SPLAT Elt, EltSize - Temporary node to be expanded during instruction selection to optimi...
@ PPC32_GOT
GPRC = address of GLOBAL_OFFSET_TABLE.
@ ADDI_DTPREL_L
G8RC = ADDI_DTPREL_L G8RReg, Symbol - For the local-dynamic TLS model, produces an ADDI8 instruction ...
@ BCTRL_LOAD_TOC
CHAIN,FLAG = BCTRL(CHAIN, ADDR, INFLAG) - The combination of a bctrl instruction and the TOC reload r...
@ PPC32_PICGOT
GPRC = address of GLOBAL_OFFSET_TABLE.
@ FCFID
FCFID - The FCFID instruction, taking an f64 operand and producing and f64 value containing the FP re...
@ CR6SET
ch, gl = CR6[UN]SET ch, inglue - Toggle CR bit 6 for SVR4 vararg calls
@ LBRX
GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a byte-swapping load instruction.
@ LD_VSX_LH
VSRC, CHAIN = LD_VSX_LH CHAIN, Ptr - This is a floating-point load of a v2f32 value into the lower ha...
@ PROBED_ALLOCA
To avoid stack clash, allocation is performed by block and each block is probed.
@ ADDIS_TLSGD_HA
G8RC = ADDIS_TLSGD_HA x2, Symbol - For the general-dynamic TLS model, produces an ADDIS8 instruction ...
@ GlobalBaseReg
GlobalBaseReg - On Darwin, this node represents the result of the mflr at function entry,...
@ LXVD2X
VSRC, CHAIN = LXVD2X_LE CHAIN, Ptr - Occurs only for little endian.
@ CALL
CALL - A direct function call.
@ MTCTR
CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a MTCTR instruction.
@ TC_RETURN
TC_RETURN - A tail call return.
@ STFIWX
STFIWX - The STFIWX instruction.
@ LD_SPLAT
VSRC, CHAIN = LD_SPLAT, CHAIN, Ptr - a splatting load memory instructions such as LXVDSX,...
@ MFFS
F8RC = MFFS - This moves the FPSCR (not modeled) into the register.
@ BUILD_FP128
Direct move of 2 consecutive GPR to a VSX register.
@ VEXTS
VEXTS, ByteWidth - takes an input in VSFRC and produces an output in VSFRC that is sign-extended from...
@ VPERM
VPERM - The PPC VPERM Instruction.
@ ADDIS_TLSLD_HA
G8RC = ADDIS_TLSLD_HA x2, Symbol - For the local-dynamic TLS model, produces an ADDIS8 instruction th...
@ XXSPLTI_SP_TO_DP
XXSPLTI_SP_TO_DP - The PPC VSX splat instructions for immediates for converting immediate single prec...
@ GET_TLSLD_ADDR
x3 = GET_TLSLD_ADDR x3, Symbol - For the local-dynamic TLS model, produces a call to __tls_get_addr(s...
@ ADDI_TLSGD_L
x3 = ADDI_TLSGD_L G8RReg, Symbol - For the general-dynamic TLS model, produces an ADDI8 instruction t...
@ DYNAREAOFFSET
This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to compute an offset from native ...
@ QVALIGNI
QVALIGNI = This corresponds to the QPX qvaligni instruction.
@ FP_EXTEND_HALF
FP_EXTEND_HALF(VECTOR, IDX) - Custom extend upper (IDX=0) half or lower (IDX=1) half of v4f32 to v2f6...
@ RET_FLAG
Return with a flag operand, matched by 'blr'.
@ CMPB
The CMPB instruction (takes two operands of i32 or i64).
@ VECSHL
VECSHL - The PPC vector shift left instruction.
@ ADDI_TLSLD_L
x3 = ADDI_TLSLD_L G8RReg, Symbol - For the local-dynamic TLS model, produces an ADDI8 instruction tha...
@ FADDRTZ
F8RC = FADDRTZ F8RC, F8RC - This is an FADD done with rounding towards zero.
@ XSMAXCDP
XSMAXCDP, XSMINCDP - C-type min/max instructions.
@ SRA_ADDZE
The combination of sra[wd]i and addze used to implemented signed integer division by a power of 2.
@ EXTSWSLI
EXTSWSLI = The PPC extswsli instruction, which does an extend-sign word and shift left immediate.
@ STXVD2X
CHAIN = STXVD2X CHAIN, VSRC, Ptr - Occurs only for little endian.
@ QVESPLATI
QVESPLATI = This corresponds to the QPX qvesplati instruction.
@ UINT_VEC_TO_FP
Extract a subvector from unsigned integer vector and convert to FP.
@ MFBHRBE
GPRC, CHAIN = MFBHRBE CHAIN, Entry, Dummy - Move from branch history rolling buffer entry.
@ FCFIDU
Newer FCFID[US] integer-to-floating-point conversion instructions for unsigned integers and single-pr...
@ FSEL
FSEL - Traditional three-operand fsel node.
@ SWAP_NO_CHAIN
An SDNode for swaps that are not associated with any loads/stores and thereby have no chain.
@ LOAD_VEC_BE
VSRC, CHAIN = LOAD_VEC_BE CHAIN, Ptr - Occurs only for little endian.
@ LFIWAX
GPRC, CHAIN = LFIWAX CHAIN, Ptr - This is a floating-point load which sign-extends from a 32-bit inte...
@ STBRX
CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a byte-swapping store instruction.
@ LD_GOT_TPREL_L
G8RC = LD_GOT_TPREL_L Symbol, G8RReg - Used by the initial-exec TLS model, produces a LD instruction ...
@ MFVSR
Direct move from a VSX register to a GPR.
@ Hi
Hi/Lo - These represent the high and low 16-bit parts of a global address respectively.
Predicate
Predicate - These are "(BI << 5) | BO" for various predicates.
SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG)
get_VSPLTI_elt - If this is a build_vector of constants which can be formed by using a vspltis[bhw] i...
bool isXXBRDShuffleMask(ShuffleVectorSDNode *N)
isXXBRDShuffleMask - Return true if this is a shuffle mask suitable for a XXBRD instruction.
FastISel * createFastISel(FunctionLoweringInfo &FuncInfo, const TargetLibraryInfo *LibInfo)
bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, unsigned ShuffleKind, SelectionDAG &DAG)
isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for a VRGH* instruction with the ...
bool isVPKUDUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, SelectionDAG &DAG)
isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a VPKUDUM instruction.
bool isVMRGEOShuffleMask(ShuffleVectorSDNode *N, bool CheckEven, unsigned ShuffleKind, SelectionDAG &DAG)
isVMRGEOShuffleMask - Return true if this is a shuffle mask suitable for a VMRGEW or VMRGOW instructi...
bool isXXBRQShuffleMask(ShuffleVectorSDNode *N)
isXXBRQShuffleMask - Return true if this is a shuffle mask suitable for a XXBRQ instruction.
bool isXXBRWShuffleMask(ShuffleVectorSDNode *N)
isXXBRWShuffleMask - Return true if this is a shuffle mask suitable for a XXBRW instruction.
bool isXXPERMDIShuffleMask(ShuffleVectorSDNode *N, unsigned &ShiftElts, bool &Swap, bool IsLE)
isXXPERMDIShuffleMask - Return true if this is a shuffle mask suitable for a XXPERMDI instruction.
bool isXXBRHShuffleMask(ShuffleVectorSDNode *N)
isXXBRHShuffleMask - Return true if this is a shuffle mask suitable for a XXBRH instruction.
unsigned getSplatIdxForPPCMnemonics(SDNode *N, unsigned EltSize, SelectionDAG &DAG)
getSplatIdxForPPCMnemonics - Return the splat index as a value that is appropriate for PPC mnemonics ...
bool isXXSLDWIShuffleMask(ShuffleVectorSDNode *N, unsigned &ShiftElts, bool &Swap, bool IsLE)
isXXSLDWIShuffleMask - Return true if this is a shuffle mask suitable for a XXSLDWI instruction.
int isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind, SelectionDAG &DAG)
isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift amount, otherwise return -1.
bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, unsigned ShuffleKind, SelectionDAG &DAG)
isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for a VRGL* instruction with the ...
int isQVALIGNIShuffleMask(SDNode *N)
If this is a qvaligni shuffle mask, return the shift amount, otherwise return -1.
bool isXXINSERTWMask(ShuffleVectorSDNode *N, unsigned &ShiftElts, unsigned &InsertAtByte, bool &Swap, bool IsLE)
isXXINSERTWMask - Return true if this VECTOR_SHUFFLE can be handled by the XXINSERTW instruction intr...
bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize)
isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand specifies a splat of a singl...
bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, SelectionDAG &DAG)
isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a VPKUWUM instruction.
bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, SelectionDAG &DAG)
isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a VPKUHUM instruction.
@ XTY_ER
External reference.
This class represents lattice values for constants.
constexpr bool isUInt< 16 >(uint64_t x)
bool isNullConstant(SDValue V)
Returns true if V is a constant integer zero.
SDValue peekThroughBitcasts(SDValue V)
Return the non-bitcasted source operand of V if it exists.
bool CC_PPC32_SVR4_ByVal(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
bool isAligned(Align Lhs, uint64_t SizeInBytes)
Checks that SizeInBytes is a multiple of the alignment.
bool isIntS16Immediate(SDNode *N, int16_t &Imm)
isIntS16Immediate - This method tests to see if the node is either a 32-bit or 64-bit immediate,...
bool CC_PPC32_SVR4_VarArg(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
bool isAcquireOrStronger(AtomicOrdering ao)
constexpr bool isPowerOf2_64(uint64_t Value)
Return true if the argument is a power of two > 0 (64 bit edition.)
constexpr bool isInt< 16 >(int64_t x)
uint32_t FloatToBits(float Float)
This function takes a float and returns the bit equivalent 32-bit integer.
unsigned M1(unsigned Val)
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
uint64_t PowerOf2Floor(uint64_t A)
Returns the power of two which is less than or equal to the given value.
bool RetCC_PPC_Cold(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
bool convertToNonDenormSingle(APInt &ArgAPInt)
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
unsigned countTrailingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0's from the least significant bit to the most stopping at the first 1.
bool CC_PPC32_SVR4(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
ArrayRef< T > makeArrayRef(const T &OneElt)
Construct an ArrayRef from a single element.
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
bool RetCC_PPC(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
AtomicOrdering
Atomic ordering for LLVM's memory model.
@ Mod
The access may modify the value stored in memory.
@ Z
zlib style complession
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
auto count(R &&Range, const E &Element)
Wrapper function around std::count to count the number of times an element Element occurs in the give...
constexpr uint64_t MinAlign(uint64_t A, uint64_t B)
A and B are either alignments or offsets.
unsigned M0(unsigned Val)
ConstantSDNode * isConstOrConstSplat(SDValue N, bool AllowUndefs=false, bool AllowTruncation=false)
Returns the SDNode if it is a constant splat BuildVector or constant int.
constexpr int32_t SignExtend32(uint32_t X)
Sign-extend the number in the bottom B bits of X to a 32-bit integer.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
constexpr unsigned BitWidth
bool isReleaseOrStronger(AtomicOrdering ao)
constexpr int64_t SignExtend64(uint64_t x)
Sign-extend the number in the bottom B bits of X to a 64-bit integer.
bool isAllOnesConstant(SDValue V)
Returns true if V is an integer constant with all bits set.
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
static const fltSemantics & IEEEsingle() LLVM_READNONE
static constexpr roundingMode rmNearestTiesToEven
static const fltSemantics & PPCDoubleDouble() LLVM_READNONE
This struct is a compact representation of a valid (non-zero power of two) alignment.
uint64_t value() const
This is a hole in the type system and should not be abused.
EVT changeVectorElementTypeToInteger() const
Return a vector with the same number of elements as this vector, but with the element type converted ...
TypeSize getScalarSizeInBits() const
TypeSize getStoreSize() const
Return the number of bytes overwritten by a store of the specified value type.
bool isSimple() const
Test if the given EVT is simple (as opposed to being extended).
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements, bool IsScalable=false)
Returns the EVT that represents a vector NumElements in length, where each element is of type VT.
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
std::string getEVTString() const
This function returns value type as a string, e.g. "i32".
bool isVector() const
Return true if this is a vector value type.
EVT getScalarType() const
If this is a vector type, return the element type, otherwise return this.
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
EVT getVectorElementType() const
Given a vector type, return the type of each element.
bool isScalarInteger() const
Return true if this is an integer, but not a vector.
unsigned getVectorNumElements() const
Given a vector type, return the number of elements it contains.
bool isInteger() const
Return true if this is an integer or a vector integer type.
OutputArg - This struct carries flags and a value for a single outgoing (actual) argument or outgoing...
void resetAll()
Resets the known state of all bits.
This class contains a discriminated union of information about pointers in memory operands,...
static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
static MachinePointerInfo getConstantPool(MachineFunction &MF)
Return a MachinePointerInfo record that refers to the constant pool.
MachinePointerInfo getWithOffset(int64_t O) const
static MachinePointerInfo getGOT(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a GOT entry.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
Structure that collects some common arguments that get passed around between the functions for call l...
These are IR-level optimization flags that may be propagated to SDNodes.
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
This contains information for each constraint that we are lowering.
This structure contains all information that is necessary for lowering calls.
SmallVector< ISD::InputArg, 32 > Ins
SmallVector< ISD::OutputArg, 32 > Outs
SmallVector< SDValue, 32 > OutVals